JPH0381643U - - Google Patents
Info
- Publication number
- JPH0381643U JPH0381643U JP1989142168U JP14216889U JPH0381643U JP H0381643 U JPH0381643 U JP H0381643U JP 1989142168 U JP1989142168 U JP 1989142168U JP 14216889 U JP14216889 U JP 14216889U JP H0381643 U JPH0381643 U JP H0381643U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- ceramic substrate
- multilayer ceramic
- semiconductor integrated
- surface layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 claims description 6
- 229910000679 solder Inorganic materials 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000010410 layer Substances 0.000 claims 3
- 239000002344 surface layer Substances 0.000 claims 3
- 238000005476 soldering Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
Description
第1図、第2図はこの考案のフエイスダウンボ
ンデイング構造を示す断面図、第3図、第4図は
従来のフエイスダウンボンデイング構造を示す断
面図である。図において、1……半導体集積回路
チツプ、2……半田バンプ、3,10……多層セ
ラミツク基板、4……内層パターン、5……表面
パターン、6……半田付けパツドパターン、7…
…バイアホール、11……バンプ挿入穴、12…
…内層半田付けパツドパターンである。なお、図
中同一符号は同一または相当部分を示す。
ンデイング構造を示す断面図、第3図、第4図は
従来のフエイスダウンボンデイング構造を示す断
面図である。図において、1……半導体集積回路
チツプ、2……半田バンプ、3,10……多層セ
ラミツク基板、4……内層パターン、5……表面
パターン、6……半田付けパツドパターン、7…
…バイアホール、11……バンプ挿入穴、12…
…内層半田付けパツドパターンである。なお、図
中同一符号は同一または相当部分を示す。
Claims (1)
- 突出した半田バンプを有する半導体集積回路チ
ツプと、複数のセラミツクシートを重ねた構成の
多層セラミツク基板において、この多層セラミツ
ク基板は表層のみ、あるいは表層から数層を貫通
する穴を有し、この穴の底面部に、内層に形成さ
れた半田付けパツドを有し、前記の半導体集積回
路チツプの半田バンプと前記の多層セラミツク基
板の内層の半田付けパツドとが半田付けしてあり
、前記の半導体集積回路チツプの本体表面が、前
記の多層セラミツク基板の表層の表面に密着した
構造になつていることを特徴とする混成集積回路
装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989142168U JPH0381643U (ja) | 1989-12-08 | 1989-12-08 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989142168U JPH0381643U (ja) | 1989-12-08 | 1989-12-08 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0381643U true JPH0381643U (ja) | 1991-08-21 |
Family
ID=31689008
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1989142168U Pending JPH0381643U (ja) | 1989-12-08 | 1989-12-08 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0381643U (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009246300A (ja) * | 2008-03-31 | 2009-10-22 | Tdk Corp | 表面実装部品およびその製造方法ならびに実装方法 |
-
1989
- 1989-12-08 JP JP1989142168U patent/JPH0381643U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009246300A (ja) * | 2008-03-31 | 2009-10-22 | Tdk Corp | 表面実装部品およびその製造方法ならびに実装方法 |