JPH0381300B2 - - Google Patents
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- Publication number
- JPH0381300B2 JPH0381300B2 JP56040339A JP4033981A JPH0381300B2 JP H0381300 B2 JPH0381300 B2 JP H0381300B2 JP 56040339 A JP56040339 A JP 56040339A JP 4033981 A JP4033981 A JP 4033981A JP H0381300 B2 JPH0381300 B2 JP H0381300B2
- Authority
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- Japan
- Prior art keywords
- gate
- film
- conductivity type
- region
- lower layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 16
- 239000012535 impurity Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 25
- 229920002120 photoresistant polymer Polymers 0.000 description 15
- 230000015556 catabolic process Effects 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Description
【発明の詳細な説明】
本発明は高耐圧高周波MOSFET（金属酸化物
半導体電解効果トランジスタ）に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high voltage, high frequency MOSFET (metal oxide semiconductor field effect transistor).
高耐圧MOSFETを製造するには、Si（シリコ
ン）半導体単結晶基板（ウエハ）の表面に熱酸化
による薄いSiO2膜をゲート絶縁膜として形成し、
このSiO2膜上に例えばMo（モリブデン）等の導
体からなるゲートを形成した後、このゲートをマ
スクとしてゲートの形成されない基板表面にイオ
ン打込み等により不純物を導入して高耐圧化層を
形成し、ゲートと高耐圧化層の一部をマスク材で
覆つた状態で高濃度の不純物を基板表面にデポジ
ツト拡散することによりソース、ドレイン領域を
自己整合的に形成する方法が採用されている。 To manufacture a high-voltage MOSFET, a thin SiO 2 film is formed as a gate insulating film by thermal oxidation on the surface of a Si (silicon) semiconductor single crystal substrate (wafer).
After forming a gate made of a conductor such as Mo (molybdenum) on this SiO 2 film, using this gate as a mask, impurities are introduced into the substrate surface where the gate is not formed by ion implantation or the like to form a high breakdown voltage layer. A method has been adopted in which the source and drain regions are formed in a self-aligned manner by depositing and diffusing highly concentrated impurities onto the substrate surface while covering the gate and a portion of the high breakdown voltage layer with a mask material.
ところで高周波電流に使用する高耐圧
MOSFETではチヤネル長（ゲート長）LCHが２〜
3μｍと微小に形成する必要があり、ドレイン側
の高耐圧化層を形成した後、この上を絶縁材から
なるマスクを覆つてソース、ドレインのデボジツ
ト拡散を行なう場合に、微小なゲート上から絶縁
材がソース側にはみ出し、ゲートとソースのオー
バーラツプ容量（COV）ができ、入力容量（Ciss）
が大幅に増加することにより高周波特性が低下す
る。又、さらにソース側にも高耐圧化層ができる
ためソース抵抗Rsが増加してgmを低下させる。
ソース抵抗部を3μｍとすれば、幅Ｗ＝４cmのチ
ツプでRS＝0.4Ω程度になり、gm＝1sの素子では
gm＝0.7sに低下し、抵抗がばらつくことで特性
のばらつきを生じ高周波高耐圧素子として不適当
である。 By the way, high voltage resistance used for high frequency current
For MOSFET, the channel length (gate length) L CH is 2~
It needs to be formed as small as 3 μm, and after forming a high breakdown voltage layer on the drain side, when deposit diffusion of the source and drain is performed by covering this layer with a mask made of an insulating material, it is necessary to deposit insulation from the top of the gate. The material protrudes to the source side, creating an overlap capacitance (C OV ) between the gate and source, and increasing the input capacitance (C iss ).
As a result, the high frequency characteristics deteriorate due to the large increase in . Furthermore, since a high breakdown voltage layer is formed on the source side, the source resistance R s increases and gm decreases.
If the source resistance part is 3 μm, R S = approximately 0.4 Ω for a chip with width W = 4 cm, and for a device with gm = 1 s.
gm = 0.7s, and the resistance varies, causing variations in characteristics, making it unsuitable as a high-frequency, high-voltage device.
本発明は上記した従来技術の欠点を取除くため
になされたものであり、その目的とするところは
入力容量が小さく、高gmの高周波高出力
MOSFETの製造法を提供にある。 The present invention has been made in order to eliminate the drawbacks of the prior art described above, and its purpose is to provide a high frequency, high output with small input capacitance and high GM.
Provides a method for manufacturing MOSFETs.
以下本発明をMOSFETのプロセスの実施例に
そつて具体的に説明する。 The present invention will be specifically described below with reference to embodiments of MOSFET processes.
第１図ａ〜ｈは本発明をＮチヤネルMOSFET
に適用した一実施例の製造ブロセスを示す。 Figures 1a to 1h show the present invention as an N-channel MOSFET.
The manufacturing process of one example applied to is shown below.
(a) P-型Si半導体基板（ウエハ）１を用意し、
ホトレジスト処理した酸化膜（SiO2）２をマ
スクにしてＰ（リン）不純物のデポジシヨン及
び引伸拡散を行ないソース、ドレイン領域とな
るN1 +層３，４を形成する。これらのN1 +層の
表面不純物濃度は〜1020atomscm-3程度とする。(a) Prepare a P - type Si semiconductor substrate (wafer) 1,
Using a photoresist-treated oxide film (SiO 2 ) 2 as a mask, P (phosphorous) impurities are deposited and stretched to form N 1 + layers 3 and 4 that will become source and drain regions. The surface impurity concentration of these N 1 + layers is approximately 10 20 atoms cm -3 .
(b) マスクに使用したSiO2膜をエツチ除去した
後、ゲート酸化を行なつて薄い（500〜1000Å）
酸化膜５を形成し、この上にゲートとなるMo
膜６を約4000Å厚に形成し、さらにこの上に多
結晶Si膜７を約4000Å厚に形成する。なお、上
記多結晶Si膜７の代りにSOG（スピンオングラ
ス）＋SiO2のごとき無機性ガラスを形成しても
よい。又、ゲートとしてはMcの代りに多結晶
Siを使用しても良く、その場合はその上に形成
する材料としてSiO2，Si3N4のごとき絶縁膜を
用いる。(b) After removing the SiO 2 film used as a mask, gate oxidation is performed to make it thin (500-1000 Å).
An oxide film 5 is formed on which Mo is deposited to form the gate.
A film 6 is formed to a thickness of about 4000 Å, and a polycrystalline Si film 7 is further formed thereon to a thickness of about 4000 Å. Note that, instead of the polycrystalline Si film 7, an inorganic glass such as SOG (spin-on glass)+SiO 2 may be formed. Also, as a gate, polycrystalline is used instead of Mc.
Si may be used, and in that case, an insulating film such as SiO 2 or Si 3 N 4 is used as the material formed thereon.
(c) ホトレジスト処理によるマスク（図示せず）
を使用し、多結晶Si及びMo膜の一部をエツチ
除去して、ポリSi−Moの２層のゲート６ａ，
７ａを形成する。このときのゲートの流さl1は
４〜5μｍとする。(c) Mask by photoresist treatment (not shown)
A portion of the polycrystalline Si and Mo films is etched away to form a two-layer gate 6a, made of polySi-Mo.
Form 7a. The gate current l1 at this time is 4 to 5 μm.
(d) ゲートの一部からドレイン側にかけてホトレ
ジスト膜８で覆い、これをマスクとしてＰ（リ
ン）又はAs（ヒ素）をイオン打込みし、ゲート
とソースとの間の基板表面にn2 +層９を形成す
る。このときのN2 +層の不純物濃度は５×
1014atoms／cm2程度とする。(d) A part of the gate to the drain side is covered with a photoresist film 8, and using this as a mask, ions of P (phosphorus) or As (arsenic) are implanted to form an n 2 + layer 9 on the substrate surface between the gate and the source. form. The impurity concentration of the N 2 + layer at this time is 5×
The amount should be approximately 10 14 atoms/cm 2 .
(e) 上記ホトレジスト膜８を除去し、今度は反対
のソース側をホトレジスト膜１０で覆い、これ
をマスクとしてHCl，HNO3系エツチ液でMo
層６ａの側面を深さd2μｍ程度にサイドエツチ
する。(e) Remove the photoresist film 8, cover the opposite source side with a photoresist film 10, and use this as a mask to remove Mo with HCl, HNO 3 based etchant.
Side-etch the layer 6a to a depth of about d2 μm.
(f) ホトレジスト膜１０を除去し、HF系エツチ
液で多結晶Si膜７ａをエツチオフする。前工程
のMo側面エツチでMoゲート長l2は2μｍ程度と
なる。このMoゲート６ａをマスクとして低濃
度のＰ（リン）又はAs（ヒ素）をイオン打込み
し、ゲートとドレインの間の基板表面に高耐圧
化層としてN3 -層１１を形成する。このN3 -層
１１の表面不純物濃度は２〜2.5×1012／cm2と
する。なおこのときN2 +層９にもＰ等が導入さ
れ、若干濃度が高くなる。(f) The photoresist film 10 is removed, and the polycrystalline Si film 7a is etched off using an HF-based etchant. By etching the Mo side surface in the previous process, the Mo gate length l2 becomes approximately 2 μm. Using this Mo gate 6a as a mask, ions of low concentration P (phosphorus) or As (arsenic) are implanted to form an N 3 − layer 11 as a high breakdown voltage layer on the substrate surface between the gate and the drain. The surface impurity concentration of this N 3 − layer 11 is 2 to 2.5×10 12 /cm 2 . Note that at this time, P and the like are also introduced into the N 2 + layer 9, and the concentration becomes slightly higher.
(g) この後、通常のMoゲートMOSFETのプロ
セスに従い、例えば全面に層間絶縁膜として
PSG（リン・シリケートガラス）膜１２を形成
し、ソースドレイン部にコンタクトホトエツチ
を行なう。(g) After this, follow the normal Mo gate MOSFET process, for example, as an interlayer insulating film on the entire surface.
A PSG (phosphorus silicate glass) film 12 is formed, and contact photoetching is performed on the source and drain portions.
(h) 全面にAl（アルミニウム）を蒸着し、次いで
ホトエツチによりAlの不要部を除去してソー
ス、ドレインにオーミツクコンタクトするAl
電極１３，１４を形成する。Al電極の一部は
ゲートを覆うフイールドプレートとして形成
し、他の一部は配線としてPSG膜上に延びる。(h) Al (aluminum) is vapor-deposited on the entire surface, and unnecessary parts of Al are removed by photo-etching to make ohmic contact with the source and drain.
Electrodes 13 and 14 are formed. A part of the Al electrode is formed as a field plate covering the gate, and the other part extends on the PSG film as a wiring.
以上実施例を述べた本発明によれば、工程(d)，
(e)でゲートを含めてホトレジストで覆い、ゲート
の一部を露出するようにホトレジストを加工する
際にゲートの長さl1を充分に大きくとつてあるか
ら、ホトレジスト誤差によるオーバーエツチやオ
ーバーラツプは生じることなく自己整合的にゲー
トの片側の基板への不純物導入が可能となる。
又、工程(e)によりソースとゲートの間の基板表面
に高濃度の不純物導入が可能となり、ソースとゲ
ートのオーバーラツプ容量COVをなくすことがで
き、入力容量Ciss増加による高周波特性の低下を
防止できる。本発明によれば、工程(e)でMoゲー
トの側面エツチを行なうことによりゲート長l2を
短く形成することが可能となり、チヤネル長LCH
のばらつきをなくし、出力特性のばらつきをなく
して高周波高耐圧素子が実現できる。 According to the present invention, the embodiments of which have been described above, step (d),
In (e), when covering the gate with photoresist and processing the photoresist to expose a part of the gate, the length of the gate l1 is made sufficiently large, so overetching and overlap due to photoresist errors are avoided. It becomes possible to introduce impurities into the substrate on one side of the gate in a self-aligned manner without causing any formation of impurities.
In addition, step (e) makes it possible to introduce high-concentration impurities into the substrate surface between the source and gate, eliminating the overlap capacitance C OV between the source and gate, and reducing the deterioration of high frequency characteristics due to an increase in input capacitance C iss . It can be prevented. According to the present invention, by performing side etching of the Mo gate in step (e), it is possible to form a short gate length l2 , and the channel length LCH
By eliminating variations in output characteristics and eliminating variations in output characteristics, it is possible to realize a high-frequency, high-voltage device.
第２図ａ〜ｄは本発明をＮチヤネルMOSFET
に適用した他の実施例の製造プロセスの一部を示
す。この実施例では前記第１図のａ〜ｄに対応す
る工程は全く同じ工程となるから省略し、第１図
ｄ工程を第２図ａ工程として以下説明する。 Figures 2 a to d show the present invention as an N-channel MOSFET.
A part of the manufacturing process of another example applied to is shown. In this embodiment, the steps a to d in FIG. 1 are the same and are therefore omitted, and the step d in FIG. 1 will be described below as the step a in FIG. 2.
(a) ゲート長l1＝4μｍ程度のMo−多結晶Siゲー
ト６ａ，７ａの一部からドレイン４側にかけて
ホトレジスト膜８で覆い、Ｐ（リン）等のイオ
ン打込みによりゲートとソースの間の基板１表
面にN2 +層９（N2i〜５×1014atoms／cm2）を形
成する。(a) Mo-polycrystalline Si gates 6a and 7a with a gate length l 1 = about 4 μm are covered with a photoresist film 8 from a part to the drain 4 side, and a substrate between the gate and source is formed by implanting ions such as P (phosphorous). An N 2 + layer 9 (N 2 i - 5×10 14 atoms/cm 2 ) is formed on one surface.
(b) 上記ホトレジスト膜８を除去し、HCl，
HNO3系エツチ液でMoゲートの両側面を深さ
0.5〜1μｍ程度にサイドエツチする。(b) Remove the photoresist film 8, add HCl,
Depth both sides of the Mo gate with HNO 3 etchant.
Side etch to about 0.5 to 1 μm.
(c) 多結晶Si膜７ａをHF系エツチ液でエツチオ
フする。全工程のMo側面エツチでMoゲート
長l2は2μｍ程度となる。このMoゲート６ａを
マスクとして低濃度のＰ又はAsイオン打込み
し、ゲートとN2 +層９ゲートとN1 +層（ドレイ
ン）４との間の基板表面に高耐圧化層として
N3 -層１１（N3i2〜５×1014atoms／cm2）を形
成する。(c) Etch off the polycrystalline Si film 7a with an HF-based etchant. The Mo gate length l 2 is approximately 2 μm due to Mo side etching in all processes. Using this Mo gate 6a as a mask, low concentration P or As ions are implanted to form a high breakdown voltage layer on the substrate surface between the gate and N 2 + layer 9 and the gate and N 1 + layer (drain) 4.
An N 3 − layer 11 (N 3 i2 to 5×10 14 atoms/cm 2 ) is formed.
(d) この後、通のMoゲートMOSFETのプロセ
スに従い、PSG膜１２形成、コンタクトホト
エツチ、Al蒸着、電極１３，１４、配線形成
により同図のMOSFETを得る。(d) After this, the MOSFET shown in the figure is obtained by forming the PSG film 12, contact photo-etching, Al vapor deposition, electrodes 13, 14, and wiring according to the conventional Mo gate MOSFET process.
以上実施例で述べた本発明によれば、工程ａで
ゲートの一部を露出するようにホトレジストを加
工する際にゲートの長さl1を充分に大きくとつて
あるからホトレジスト誤差によるオーバーラツプ
等を生じることなく自己整合的にゲートの片側の
基板への不純物導入が可能となり、入力抵抗Ciss
を低減できる。又、工程(b)でMoゲートの側面エ
ツチを行なうことによりゲートl2を短かく形成す
ることが可能となり、チヤネル長LCHのばらつき
をなくし高周波特性が得られる。なお、ゲートと
ソース側のN2 +層とゲートとの間の高耐圧N3 -層
１１はわずかであり、ソース抵抗RSは0.9〜1μｍ
程度であり、N2 +層９の再拡散を考えると無視で
きることになり、高gmが達成できる。 According to the present invention described in the above embodiments, when processing the photoresist to expose a part of the gate in step a, the gate length l1 is set sufficiently large, so that overlaps due to photoresist errors can be avoided. It is possible to introduce impurities into the substrate on one side of the gate in a self-aligned manner without causing any
can be reduced. Furthermore, by etching the side surfaces of the Mo gate in step (b), it becomes possible to form the gate L2 short, eliminating variations in the channel length L CH and providing high frequency characteristics. Note that the high breakdown voltage N 3 - layer 11 between the N 2 + layer on the gate and source side and the gate is small, and the source resistance R S is 0.9 to 1 μm.
This can be ignored considering the re-diffusion of the N 2 + layer 9, and a high gm can be achieved.
本発明は前記実施例に限定されることなく、こ
れ以外の変形実施が多く考えられる。 The present invention is not limited to the above-mentioned embodiments, and many other modifications are possible.
第１図ａ〜ｈは本発明によるMOSFETの製造
プロセスの一実施例を示す工程断面図である。第
２図ａ〜ｄは本発明によるMOSFETの製造プロ
セスの他の実施例を示す一部工程断面図である。
１……P-型Si基板、２……酸化膜、３……N+
ソース、４……N+ドレイン、５……ゲート酸化
膜、６……Mo膜、７……多結晶Si膜、８……ホ
トレジスト、９……N2 +層、１０……ホトレジス
ト、１１……N3 -（高耐圧化）層、１２……PSG
膜、１３，１４……Al電極。
FIGS. 1a to 1h are cross-sectional views showing an embodiment of the MOSFET manufacturing process according to the present invention. FIGS. 2a to 2d are partial process cross-sectional views showing another embodiment of the MOSFET manufacturing process according to the present invention. 1...P - type Si substrate, 2...Oxide film, 3...N +
Source, 4...N + drain, 5...gate oxide film, 6...Mo film, 7...polycrystalline Si film, 8...photoresist, 9... N2 + layer, 10...photoresist, 11... ...N 3 - (high voltage resistance) layer, 12...PSG
Membrane, 13, 14... Al electrode.
Claims (1)
してソースおよびドレインとなる一対の第２導電
型領域を形成し、該第２導電型領域間の基板表面
の一部の上に、ゲート酸化膜を介して導電性の下
層膜と該下層膜と異なる物質からなる上層膜とを
形成し、これら下層膜および上層膜を積層した状
態で、前記下層膜の一方の端部と該端部に対向す
る前記第２導電型領域の一方との間の基板表面に
第２導電型の不純物を導入することによつて、前
記下層膜の一方の端部から前記一方の第２導電型
領域へ延在する第３の領域を形成し、前記上層膜
をマスクとして前記下層膜を側面エツチし、側面
エツチされた少なくとも前記下層膜の一方の端部
と前記第３の領域との間の基板表面に第２導電型
の不純物を導入することによつて、前記下層膜の
側面エツチされた前記端部から前記第３の領域へ
延在し、かつ前記第３の領域と抵抗率が異なる第
４の領域を形成することを特徴とするMOS半導
体装置の製造法。1. A pair of second conductivity type regions that are spaced apart from each other and serve as a source and a drain are formed on the main surface of the first conductivity type semiconductor substrate, and gate oxidation is performed on a part of the substrate surface between the second conductivity type regions. A conductive lower layer film and an upper layer film made of a material different from the lower layer film are formed through the film, and in a state where the lower layer film and the upper layer film are laminated, one end of the lower film and the end thereof are formed. By introducing a second conductivity type impurity into the surface of the substrate between one of the second conductivity type regions facing each other, it is possible to spread the impurity from one end of the lower film to the one second conductivity type region. forming a third region where the lower layer is etched, side-etching the lower layer using the upper layer as a mask, and etching the substrate surface between at least one end of the side-etched lower layer and the third region; By introducing impurities of the second conductivity type, a fourth region extends from the side-etched end of the lower layer film to the third region and has a resistivity different from that of the third region. A method for manufacturing a MOS semiconductor device characterized by forming a region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4033981A JPS57155776A (en) | 1981-03-23 | 1981-03-23 | Mos semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4033981A JPS57155776A (en) | 1981-03-23 | 1981-03-23 | Mos semiconductor device and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57155776A JPS57155776A (en) | 1982-09-25 |
| JPH0381300B2 true JPH0381300B2 (en) | 1991-12-27 |
Family
ID=12577869
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4033981A Granted JPS57155776A (en) | 1981-03-23 | 1981-03-23 | Mos semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57155776A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54987A (en) * | 1977-06-06 | 1979-01-06 | Hitachi Ltd | Manufacture for semiconductor device |
-
1981
- 1981-03-23 JP JP4033981A patent/JPS57155776A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54987A (en) * | 1977-06-06 | 1979-01-06 | Hitachi Ltd | Manufacture for semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57155776A (en) | 1982-09-25 |
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