JPH0376779B2 - - Google Patents
Info
- Publication number
- JPH0376779B2 JPH0376779B2 JP59237220A JP23722084A JPH0376779B2 JP H0376779 B2 JPH0376779 B2 JP H0376779B2 JP 59237220 A JP59237220 A JP 59237220A JP 23722084 A JP23722084 A JP 23722084A JP H0376779 B2 JPH0376779 B2 JP H0376779B2
- Authority
- JP
- Japan
- Prior art keywords
- resin
- pot
- tablet
- molding
- mold
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Moulds For Moulding Plastics Or The Like (AREA)
- Injection Moulding Of Plastics Or The Like (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59237220A JPS61115330A (ja) | 1984-11-10 | 1984-11-10 | 半導体装置の製造方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59237220A JPS61115330A (ja) | 1984-11-10 | 1984-11-10 | 半導体装置の製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61115330A JPS61115330A (ja) | 1986-06-02 |
| JPH0376779B2 true JPH0376779B2 (OSRAM) | 1991-12-06 |
Family
ID=17012158
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59237220A Granted JPS61115330A (ja) | 1984-11-10 | 1984-11-10 | 半導体装置の製造方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61115330A (OSRAM) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2592753B2 (ja) * | 1992-09-18 | 1997-03-19 | 日東電工株式会社 | 半導体封止用樹脂タブレット |
| US6173490B1 (en) * | 1997-08-20 | 2001-01-16 | National Semiconductor Corporation | Method for forming a panel of packaged integrated circuits |
| JP2014086609A (ja) * | 2012-10-25 | 2014-05-12 | Renesas Electronics Corp | 半導体装置の製造方法 |
-
1984
- 1984-11-10 JP JP59237220A patent/JPS61115330A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61115330A (ja) | 1986-06-02 |
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