JPH0369230U - - Google Patents

Info

Publication number
JPH0369230U
JPH0369230U JP1989131168U JP13116889U JPH0369230U JP H0369230 U JPH0369230 U JP H0369230U JP 1989131168 U JP1989131168 U JP 1989131168U JP 13116889 U JP13116889 U JP 13116889U JP H0369230 U JPH0369230 U JP H0369230U
Authority
JP
Japan
Prior art keywords
group
semiconductor
semiconductor substrate
solder bump
connection areas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1989131168U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989131168U priority Critical patent/JPH0369230U/ja
Publication of JPH0369230U publication Critical patent/JPH0369230U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第１図は本考案の半導体装置の断面図、第２図
は第１図の概略断面図、第３図は従来の半導体装
置の断面図、第４図は半導体装置と外部基板との
接続を示す断面図である。

Claims (1)

  1. 【実用新案登録請求の範囲】 (1) 半導体素子が多数形成された実質的に矩形
    状の半導体基板と、 この半導体基板上に設けられた外部基板との接
    続領域群と、 この接続領域群に設けられた複数の金属薄膜層
    と、 この薄膜層状に設けられた半田バンプ群とを備
    え、 前記半田バンプ群は前記半導体基板上に実質的
    に矩形状に配列され、この半田バンプ群の外側に
    対応する半導体基板内には半導体素子が形成され
    ることを特徴とする半導体装置。 (2) 前記半導体素子で所定の回路を達成するた
    めに、前記半導体基板上には複数層の金属配線が
    設けられ、上層の金属配線が前記接続領域に延在
    される事を特徴とする請求項第１項記載の半導体
    装置。 (3) 前記半田バンプ群が矩形状に配列された領
    域に対応する前記半導体基板領域内には、前記半
    導体素子が実質的に存在しないことを特徴とする
    請求項第１項記載の半導体装置。
JP1989131168U 1989-11-10 1989-11-10 Pending JPH0369230U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989131168U JPH0369230U (ja) 1989-11-10 1989-11-10

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989131168U JPH0369230U (ja) 1989-11-10 1989-11-10

Publications (1)

Publication Number Publication Date
JPH0369230U true JPH0369230U (ja) 1991-07-09

Family

ID=31678691

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989131168U Pending JPH0369230U (ja) 1989-11-10 1989-11-10

Country Status (1)

Country Link
JP (1) JPH0369230U (ja)

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