JPH0361216B2 - - Google Patents

Info

Publication number
JPH0361216B2
JPH0361216B2 JP57052974A JP5297482A JPH0361216B2 JP H0361216 B2 JPH0361216 B2 JP H0361216B2 JP 57052974 A JP57052974 A JP 57052974A JP 5297482 A JP5297482 A JP 5297482A JP H0361216 B2 JPH0361216 B2 JP H0361216B2
Authority
JP
Japan
Prior art keywords
memory
common
processor
individual
page
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57052974A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58169662A (ja
Inventor
Tetsuo Nishino
Kazumi Akyoshi
Eisuke Iwabuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57052974A priority Critical patent/JPS58169662A/ja
Publication of JPS58169662A publication Critical patent/JPS58169662A/ja
Publication of JPH0361216B2 publication Critical patent/JPH0361216B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G06F11/0724—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU] in a multiprocessor or a multi-core unit
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
JP57052974A 1982-03-31 1982-03-31 システム運転方式 Granted JPS58169662A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57052974A JPS58169662A (ja) 1982-03-31 1982-03-31 システム運転方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57052974A JPS58169662A (ja) 1982-03-31 1982-03-31 システム運転方式

Publications (2)

Publication Number Publication Date
JPS58169662A JPS58169662A (ja) 1983-10-06
JPH0361216B2 true JPH0361216B2 (en, 2012) 1991-09-19

Family

ID=12929862

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57052974A Granted JPS58169662A (ja) 1982-03-31 1982-03-31 システム運転方式

Country Status (1)

Country Link
JP (1) JPS58169662A (en, 2012)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7251744B1 (en) * 2004-01-21 2007-07-31 Advanced Micro Devices Inc. Memory check architecture and method for a multiprocessor computer system
GB0805833D0 (en) * 2008-03-26 2008-04-30 Symbian Software Ltd Swap parition

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5143653A (ja) * 1974-10-11 1976-04-14 Fujitsu Ltd Akusesuseigyohoshiki

Also Published As

Publication number Publication date
JPS58169662A (ja) 1983-10-06

Similar Documents

Publication Publication Date Title
JP5265654B2 (ja) システムにおけるメモリ冗長性の制御
JPH0454260B2 (en, 2012)
JP2004252591A (ja) 計算機システム、ｉ／ｏデバイス及びｉ／ｏデバイスの仮想共有方法
JPH041374B2 (en, 2012)
JP2009211517A (ja) 仮想計算機冗長化システム
JP2004102395A (ja) メモリダンプデータの取得方法および情報処理装置、ならびにそのプログラム
EP1890229B1 (en) System controller, data processor, and input output request control method
JPH0361216B2 (en, 2012)
JPS6342294B2 (en, 2012)
JPS6134645A (ja) 二重化メモリ制御方式
JPS5914063A (ja) マイクロコンピユ−タのスタ−トアツプ方式
US6275915B1 (en) Selective memory duplication arrangement
JP2853593B2 (ja) ダウンロード装置
JPS59180897A (ja) バツテリバツクアツプメモリの二重化方式
JPH08179994A (ja) コンピュータシステム
JP2003330737A (ja) 計算機システム
JPS605369A (ja) メモリ制御方式
JPH0795311B2 (ja) 二重化処理装置
JPH0727468B2 (ja) 二重化情報処理装置
JPH05216772A (ja) メモリ管理機構
JPH0240760A (ja) 情報処理装置
KR20030068663A (ko) 이중화 보드간의 비휘발성 메모리 정보 동기화 장치 및 방법
JPH05216773A (ja) メモリ管理機構
Sicola The architecture and design of HS-series StorageWorks Array Controllers
JPS62182953A (ja) メモリアクセス制御方式