JPH035619B2 - - Google Patents

Info

Publication number
JPH035619B2
JPH035619B2 JP56099269A JP9926981A JPH035619B2 JP H035619 B2 JPH035619 B2 JP H035619B2 JP 56099269 A JP56099269 A JP 56099269A JP 9926981 A JP9926981 A JP 9926981A JP H035619 B2 JPH035619 B2 JP H035619B2
Authority
JP
Japan
Prior art keywords
data
memory
cache memory
control unit
reading
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56099269A
Other languages
English (en)
Japanese (ja)
Other versions
JPS581256A (ja
Inventor
Masaaki Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56099269A priority Critical patent/JPS581256A/ja
Publication of JPS581256A publication Critical patent/JPS581256A/ja
Publication of JPH035619B2 publication Critical patent/JPH035619B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP56099269A 1981-06-26 1981-06-26 メモリアクセス制御方式 Granted JPS581256A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56099269A JPS581256A (ja) 1981-06-26 1981-06-26 メモリアクセス制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56099269A JPS581256A (ja) 1981-06-26 1981-06-26 メモリアクセス制御方式

Publications (2)

Publication Number Publication Date
JPS581256A JPS581256A (ja) 1983-01-06
JPH035619B2 true JPH035619B2 (lt) 1991-01-28

Family

ID=14242962

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56099269A Granted JPS581256A (ja) 1981-06-26 1981-06-26 メモリアクセス制御方式

Country Status (1)

Country Link
JP (1) JPS581256A (lt)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0614031Y2 (ja) * 1985-05-21 1994-04-13 日産自動車株式会社 渦流室式デイ−ゼルエンジン

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55153024A (en) * 1979-05-15 1980-11-28 Toshiba Corp Bus control system
JPS5671129A (en) * 1979-11-15 1981-06-13 Fujitsu Ltd Data processing system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55153024A (en) * 1979-05-15 1980-11-28 Toshiba Corp Bus control system
JPS5671129A (en) * 1979-11-15 1981-06-13 Fujitsu Ltd Data processing system

Also Published As

Publication number Publication date
JPS581256A (ja) 1983-01-06

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