JPH0344818U - - Google Patents
Info
- Publication number
- JPH0344818U JPH0344818U JP10537689U JP10537689U JPH0344818U JP H0344818 U JPH0344818 U JP H0344818U JP 10537689 U JP10537689 U JP 10537689U JP 10537689 U JP10537689 U JP 10537689U JP H0344818 U JPH0344818 U JP H0344818U
- Authority
- JP
- Japan
- Prior art keywords
- layer
- insulating base
- conductive layer
- jumper chip
- overcoat layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000007747 plating Methods 0.000 claims description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Description
第１図は本考案の一実施例に係るジヤンパーチ
ツプの平面図、第２図はそのＡ−Ａ線断面図、第
３図は本考案の他の実施例に係るジヤンパーチツ
プの平面図、第４図は本考案のさらに他の実施例
に係るジヤンパーチツプの平面図、第５図は従来
のジヤンパーチツプをプリント基板のパターンに
はんだ付けした状態を示す断面図、第６図はその
平面図である。
１……絶縁基台、２……導電層、３……オーバ
ーコート層、３ａ……切欠、４……ニツケルメツ
キ層、５……はんだメツキ層。
FIG. 1 is a plan view of a jumper chip according to an embodiment of the present invention, FIG. 2 is a sectional view taken along line A-A, FIG. 3 is a plan view of a jumper chip according to another embodiment of the present invention, and FIG. 5 is a plan view of a jumper chip according to still another embodiment of the present invention, FIG. 5 is a sectional view showing a conventional jumper chip soldered to a pattern on a printed circuit board, and FIG. 6 is a plan view thereof. DESCRIPTION OF SYMBOLS 1... Insulating base, 2... Conductive layer, 3... Overcoat layer, 3a... Notch, 4... Nickel plating layer, 5... Solder plating layer.
Claims (1)
および下面両端部を抱きこんで被着した導電層と
、上記絶縁基台の上面側で上記導電層上に設けた
オーバーコート層と、上記導電層の表面で上記オ
ーバーコート層に覆われていない部分に被着した
メツキ層とを備えたジヤンパーチツプにおいて、
上記オーバーコート層の略中央部に、上記メツキ
層を露出させるための切欠を設けたことを特徴と
するジヤンパーチツプ。 A plate-shaped insulating base, a conductive layer covering the top, side and bottom ends of the insulating base, and an overcoat layer provided on the conductive layer on the top side of the insulating base. , a jumper chip comprising a plating layer deposited on a portion of the surface of the conductive layer that is not covered with the overcoat layer,
A jumper chip characterized in that a notch for exposing the plating layer is provided approximately at the center of the overcoat layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10537689U JPH0648674Y2 (en) | 1989-09-11 | 1989-09-11 | The jumper chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10537689U JPH0648674Y2 (en) | 1989-09-11 | 1989-09-11 | The jumper chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0344818U true JPH0344818U (en) | 1991-04-25 |
| JPH0648674Y2 JPH0648674Y2 (en) | 1994-12-12 |
Family
ID=31654138
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10537689U Expired - Lifetime JPH0648674Y2 (en) | 1989-09-11 | 1989-09-11 | The jumper chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0648674Y2 (en) |
-
1989
- 1989-09-11 JP JP10537689U patent/JPH0648674Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0648674Y2 (en) | 1994-12-12 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |