JPS6226074U - - Google Patents
Info
- Publication number
- JPS6226074U JPS6226074U JP11781685U JP11781685U JPS6226074U JP S6226074 U JPS6226074 U JP S6226074U JP 11781685 U JP11781685 U JP 11781685U JP 11781685 U JP11781685 U JP 11781685U JP S6226074 U JPS6226074 U JP S6226074U
- Authority
- JP
- Japan
- Prior art keywords
- adjacent
- lands
- wiring board
- printed wiring
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 claims 1
- 238000005476 soldering Methods 0.000 description 1
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
第1図はこの考案の一実施例に係るプリント配
線板の裏面構造を示す平面図、第2図はその要部
断面図、第3図は部品半田付け後のプリント配線
板の要部断面図、第4図は本案の他の実施例を示
す平面図、第5図は従来のプリント配線板の裏面
構造を示す平面図、第6図はその要部断面図、第
7図はその電子部品を半田付けした状態を示す要
部断面図である。
11……絶縁基板、12……導電パターン、1
3……レジスト層、14……ランド、20,20
,30,30……シルク印刷層。
Fig. 1 is a plan view showing the back structure of a printed wiring board according to an embodiment of this invention, Fig. 2 is a sectional view of the main part thereof, and Fig. 3 is a sectional view of the main part of the printed wiring board after soldering the components. , Fig. 4 is a plan view showing another embodiment of the present invention, Fig. 5 is a plan view showing the back structure of a conventional printed wiring board, Fig. 6 is a sectional view of its main parts, and Fig. 7 is its electronic components. FIG. 2 is a cross-sectional view of main parts showing a soldered state. 11... Insulating substrate, 12... Conductive pattern, 1
3...Resist layer, 14...Land, 20, 20
, 30, 30...Silk printing layer.
Claims (1)
数の導電パターンを設け、その導電パターンの隣
接した部分に半田レジスト層で囲われたランドを
所定の方向に並設して成るプリント配線板におい
て、前記隣接ランドの相隣接する部分表面にシル
ク印刷による層を形成したことを特徴とするプリ
ント配線板。 (2) 前記シルク印刷層が前記隣接ランド間に架
橋状に掛け渡し形成されていることを特徴とする
実用新案登録請求の範囲第1項に記載のプリント
配線板。[Claims for Utility Model Registration] (1) A plurality of adjacent and independent conductive patterns are provided on the surface of an insulating substrate, and lands surrounded by a solder resist layer are arranged in a predetermined direction in adjacent parts of the conductive patterns. 1. A printed wiring board, characterized in that a layer is formed by silk printing on the surfaces of adjacent portions of the adjacent lands. (2) The printed wiring board according to claim 1, wherein the silk printing layer is formed in a bridge-like manner between the adjacent lands.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11781685U JPS6226074U (en) | 1985-07-31 | 1985-07-31 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11781685U JPS6226074U (en) | 1985-07-31 | 1985-07-31 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6226074U true JPS6226074U (en) | 1987-02-17 |
Family
ID=31003685
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11781685U Pending JPS6226074U (en) | 1985-07-31 | 1985-07-31 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6226074U (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51132466A (en) * | 1975-05-13 | 1976-11-17 | Tokyo Purinto Kougiyou Kk | Method of manufacturing independent lands on printed wiring board |
JPS5550684A (en) * | 1978-10-06 | 1980-04-12 | Hitachi Ltd | Printed circuit board |
-
1985
- 1985-07-31 JP JP11781685U patent/JPS6226074U/ja active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51132466A (en) * | 1975-05-13 | 1976-11-17 | Tokyo Purinto Kougiyou Kk | Method of manufacturing independent lands on printed wiring board |
JPS5550684A (en) * | 1978-10-06 | 1980-04-12 | Hitachi Ltd | Printed circuit board |