JPH0342737B2 - - Google Patents

Info

Publication number
JPH0342737B2
JPH0342737B2 JP58178283A JP17828383A JPH0342737B2 JP H0342737 B2 JPH0342737 B2 JP H0342737B2 JP 58178283 A JP58178283 A JP 58178283A JP 17828383 A JP17828383 A JP 17828383A JP H0342737 B2 JPH0342737 B2 JP H0342737B2
Authority
JP
Japan
Prior art keywords
phase
clock signal
signal
output
input signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58178283A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6072345A (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP58178283A priority Critical patent/JPS6072345A/ja
Publication of JPS6072345A publication Critical patent/JPS6072345A/ja
Publication of JPH0342737B2 publication Critical patent/JPH0342737B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP58178283A 1983-09-28 1983-09-28 デイジタル信号位相同期回路 Granted JPS6072345A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58178283A JPS6072345A (ja) 1983-09-28 1983-09-28 デイジタル信号位相同期回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58178283A JPS6072345A (ja) 1983-09-28 1983-09-28 デイジタル信号位相同期回路

Publications (2)

Publication Number Publication Date
JPS6072345A JPS6072345A (ja) 1985-04-24
JPH0342737B2 true JPH0342737B2 (en, 2012) 1991-06-28

Family

ID=16045756

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58178283A Granted JPS6072345A (ja) 1983-09-28 1983-09-28 デイジタル信号位相同期回路

Country Status (1)

Country Link
JP (1) JPS6072345A (en, 2012)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH084262B2 (ja) * 1986-03-31 1996-01-17 日本電気株式会社 ビツト同期回路及び方法
JPH0728278B2 (ja) * 1986-05-19 1995-03-29 株式会社日立製作所 同期信号抽出回路
JPS63229934A (ja) * 1987-03-19 1988-09-26 Fujitsu Ltd タイミングｐｌｌ方式

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56116755U (en, 2012) * 1980-02-05 1981-09-07

Also Published As

Publication number Publication date
JPS6072345A (ja) 1985-04-24

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