JPH0330987B2 - - Google Patents
Info
- Publication number
- JPH0330987B2 JPH0330987B2 JP58157886A JP15788683A JPH0330987B2 JP H0330987 B2 JPH0330987 B2 JP H0330987B2 JP 58157886 A JP58157886 A JP 58157886A JP 15788683 A JP15788683 A JP 15788683A JP H0330987 B2 JPH0330987 B2 JP H0330987B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- film
- finger
- bonding
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 37
- 239000000758 substrate Substances 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 17
- 230000000630 rising effect Effects 0.000 claims description 4
- 229920001721 polyimide Polymers 0.000 description 11
- 238000010586 diagram Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 3
- 238000000576 coating method Methods 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 229920002050 silicone resin Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000007872 degassing Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000007779 soft material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/79—Apparatus for Tape Automated Bonding [TAB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
（技術分野）
本発明は、例えばポリイミドフイルムに設けた
デバイスホールにICチツプ等の半導体チツプを
組込むフイルムキヤリア方式を用いた半導体チツ
プの実装方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for mounting a semiconductor chip using a film carrier method in which a semiconductor chip such as an IC chip is embedded in a device hole provided in a polyimide film, for example.
（従来技術）
第１図は、従来のフイルムキヤリア方式による
アウターボンデイング前、換言すると、ボンデイ
ング法を用いて基板上に組込み実装する前の半導
体チツプの状態を示す図で、同図ａはその正面
図、同図ｂはその断面図である。図中１はICチ
ツプ等の半導体チツプであり、２は銅箔で形成さ
れ、その先端にフインガー２ａを有するフインガ
ーリードであり、更に、３は前記フインガーリー
ド２を形成したポリイミドフイルムであつて、例
えば前記フインガー２ａのピツチの乱れ、所謂バ
ラケの状態になるのを防いでいる。(Prior Art) Fig. 1 shows the state of a semiconductor chip before outer bonding using the conventional film carrier method, in other words, before it is assembled and mounted on a board using the bonding method. Figure 1B is a sectional view thereof. In the figure, 1 is a semiconductor chip such as an IC chip, 2 is a finger lead made of copper foil and has a finger 2a at its tip, and 3 is a polyimide film on which the finger lead 2 is formed. This prevents, for example, the pitch of the fingers 2a from becoming disordered, or from becoming unbalanced.
第２図、第３図は、前記第１図で示した状態に
形成した半導体チツプを、アウターボンデイング
によつて基板に組込み実装した場合の状態図で、
図中、４は接続パターン（ボンデイングパター
ン）４ａと配線パターン４a′とをその表面に形成
した基板であり、矢印はフインガー２ａと接続パ
ターン４ａとのボンデイング位置を示している。
なお、前記配線パターン４a′は、基板の実装密度
を向上させる為に採用される構成であつて、半導
体チツプの実装部分に形成されている。 FIGS. 2 and 3 are state diagrams in which the semiconductor chip formed in the state shown in FIG. 1 is assembled and mounted on a substrate by outer bonding.
In the figure, 4 is a substrate on which a connection pattern (bonding pattern) 4a and a wiring pattern 4a' are formed, and arrows indicate bonding positions between the finger 2a and the connection pattern 4a.
Note that the wiring pattern 4a' has a structure adopted to improve the mounting density of the board, and is formed on the mounting portion of the semiconductor chip.
ここで、第１図で示す半導体チツプを、アウタ
ーボンデイングによつて基板上に組込み実装した
状態を示す第２図、第３図をみると、第２図で
は、ポリイミドフイルム３に形成されたフインガ
ーリード２の部分と基板４に形成された配線パタ
ーン４a′との間隙が充分に確保されておらず、
又、第３図では、フインガーリード２が配線パタ
ーン４a′と接触しているのが理解される。したが
つて、第１図に示す状態の半導体チツプでは、ボ
ンデイング加工等の際、フインガーリードと配線
パターンとが接し、最悪で第３図の如き状態にな
る恐れがあつた。更に述べれば、前記接触する配
線パターンがそのフインガーリードが本来接続さ
れるべき接続パターンであれば影響は出ないが、
そのパターンの種類が異なるとシヨートし、した
がつて、所望の特性が得られなくなる恐れがあ
り、半導体チツプの実装面上にパターン形成し、
実用に供することは困難であつた。又、半導体チ
ツプのフインガーリードについては、その長さが
短い為、基板への実装に用いるアウターボンデイ
ング加工を行うと、その際リフローした熱は半導
体チツプ１とフインガーリード２との接続部、す
なわち、インナーボンデイング部に伝わり、ボン
デイング剥れが生じる恐れがあり、したがつて、
接続の信頼性の低下を招き、歩留りが低下する等
の問題点があつた。 Now, looking at FIGS. 2 and 3, which show the semiconductor chip shown in FIG. 1 mounted on a board by outer bonding, in FIG. A sufficient gap between the swing lead 2 and the wiring pattern 4a' formed on the substrate 4 is not secured.
Further, in FIG. 3, it can be seen that the finger lead 2 is in contact with the wiring pattern 4a'. Therefore, in the semiconductor chip in the state shown in FIG. 1, during bonding processing or the like, the finger leads and the wiring pattern may come into contact with each other, resulting in a situation as shown in FIG. 3 at worst. Furthermore, if the contacting wiring pattern is the connection pattern to which the finger lead should originally be connected, there will be no effect;
If the type of the pattern is different, the desired characteristics may not be obtained.
It was difficult to put it into practical use. Furthermore, since the finger leads of the semiconductor chip are short in length, when the outer bonding process used for mounting on the board is performed, the reflowed heat is transferred to the connection between the semiconductor chip 1 and the finger leads 2, In other words, there is a risk that it will be transmitted to the inner bonding part and cause the bonding to peel off.
There were problems such as a decrease in connection reliability and a decrease in yield.
なお、前記ボンデイング剥れを防ぐには、フイ
ンガー部分を長くすることも考えられるが、この
場合には、取り扱いにおいてフインガー部分にバ
ラケの状態が起きて基板上の配線パターンとの位
置合せが困難になつたり、あるいはアウターボン
デイングの際、そのボンデイングツールとの接触
時に位置ずれが発生し易くなる問題が生じる。 In order to prevent the bonding from peeling off, it is possible to lengthen the finger portion, but in this case, the finger portion may come apart during handling, making it difficult to align it with the wiring pattern on the board. During outer bonding, a problem arises in that positional deviation is likely to occur during contact with the bonding tool.
（発明の目的）
本発明はこのような点を考慮してなされたもの
であつて、ポリイミドフイルムに形成したフイン
ガーリードと基板に形成した配線パターンとのシ
ヨートの恐れを除去し、それとともに半導体チツ
プの実装密度の向上の得られるフイルムキヤリア
方式を用いた半導体チツプの実装方法を提供する
ことを目的とする。(Object of the Invention) The present invention has been made in consideration of the above points, and eliminates the fear of shorting between the finger leads formed on the polyimide film and the wiring pattern formed on the substrate, and The object of the present invention is to provide a method for mounting semiconductor chips using a film carrier method, which can improve the packaging density of chips.
（発明の構成）
すなわち、本発明は上記目的を達成する為に、
半導体チツプ両端に接続するフインガーリードを
２段階設置したポリイミドフイルム上に形成し、
該形成した半導体チツプの基板への実装は、両者
の間で十分な空間が形成出来るようにフインガー
リードをボンデイングすることにより行う構成と
したものである。以下、図面を用いて本発明を詳
細に説明する。(Structure of the invention) That is, in order to achieve the above object, the present invention has the following features:
Finger leads connected to both ends of the semiconductor chip are formed on a polyimide film with two stages.
The formed semiconductor chip is mounted on the substrate by bonding the finger leads so that a sufficient space can be formed between the two. Hereinafter, the present invention will be explained in detail using the drawings.
（発明の実施例）
第４図、第５図は、本発明に係る実装方法を説
明する図で、第４図はフイルムキヤリア方式によ
るアウターボンデイング前、すなわち、基板上に
組込み実装される前の半導体チツプの状態を示す
図で、同図ａはその正面図、同図ｂはその断面図
である。又、第５図は前記第４図で示した状態の
半導体チツプをアウターボンデイングにより基板
に組込み実装した場合の状態図である。図中、第
１図、第２図で示した従来の構成と異なるのは、
半導体チツプ１からのフインガーリード２を長く
形成し、しかも、途中２段のポリイミドフイル
ム、即ち中間フイルム３ａ、終端フイルム３ｂを
形成した構成である。更に、前記フインガーリー
ド２は、中間フイルム３ａでそのピツチ、パター
ン等の変更を施し、終端フイルム３ｂで基板４上
のボンデイングピツチ、換言すると接続パターン
４ａのピツチと同一（図示せず）になるように形
成されている。又、接続パターン４ａと配線パタ
ーン４a′との距離も従来のそれと較べて広くする
ことが可能である。(Embodiment of the invention) FIGS. 4 and 5 are diagrams for explaining the mounting method according to the present invention. 1 is a diagram showing the state of a semiconductor chip, in which figure a is a front view thereof, and figure b is a sectional view thereof. Further, FIG. 5 is a state diagram when the semiconductor chip shown in FIG. 4 is assembled and mounted on a substrate by outer bonding. In the figure, the differences from the conventional configuration shown in Figures 1 and 2 are as follows:
The finger leads 2 from the semiconductor chip 1 are formed long, and two layers of polyimide films, namely an intermediate film 3a and a terminal film 3b, are formed in the middle. Furthermore, the pitch, pattern, etc. of the finger leads 2 are changed using the intermediate film 3a, and the bonding pitch on the substrate 4 is made the same (not shown) as the bonding pitch on the substrate 4, in other words, the pitch of the connection pattern 4a (not shown). It is formed like this. Furthermore, the distance between the connection pattern 4a and the wiring pattern 4a' can also be made wider compared to the conventional one.
以上、第４図で示した構成の半導体チツプを、
ボンデイング法により基板に組込み実装したのが
第５図である。即ち、フインガーリード２を形成
したポリイミドフイルムとして中間フイルム３
ａ、終端フイルム３ｂを設ける。これら中間フイ
ルム３ａ、終端フイルム３ｂとの間で、フインガ
ーリード２の立上り部を形成する。この立上り部
を形成することにより、半導体チツプ１と基板４
との間に充分な空間を確保することができる。こ
の立上り部の形成は、フイルム上に搭載された半
導体チツプの打ち抜き時に同時に行えるので、特
に工数の増加という問題は生じない。 As described above, the semiconductor chip having the configuration shown in FIG.
FIG. 5 shows the device assembled and mounted on a board using the bonding method. That is, the intermediate film 3 is used as a polyimide film on which the finger leads 2 are formed.
a. A terminal film 3b is provided. A rising portion of the finger lead 2 is formed between the intermediate film 3a and the end film 3b. By forming this rising portion, the semiconductor chip 1 and the substrate 4
Sufficient space can be secured between the two. Since this rising portion can be formed at the same time as punching out the semiconductor chip mounted on the film, there is no particular problem of increased man-hours.
この後、半導体チツプ１に、その表面保護、絶
縁確保等の為に、例えばシリコン樹脂を用いてそ
の全体をコーテイングする。このコーテイング加
工には脱泡技術が用いられ、これにより前記半導
体チツプ１、フインガーリード２、および基板４
によつて形成された空間に、その空間が大きい為
前記シリコン樹脂は充分に浸透し、したがつて、
空間の確保も確実なものとなる。又、フインガー
リード２については、従来のそれと較べて長くな
り、したがつて、半導体チツプ１のアウターボン
デイングの際、この熱によるリフローによつて半
導体チツプ１とフインガーリード２とのインナー
ボンデイング部分での接続剥れが恐れがなくな
る。 Thereafter, the entire semiconductor chip 1 is coated with silicone resin, for example, in order to protect its surface and ensure insulation. A defoaming technique is used for this coating process, whereby the semiconductor chip 1, the finger leads 2, and the substrate 4
Because the space is large, the silicone resin sufficiently penetrates into the space formed by
It also ensures that space is secured. Furthermore, the finger leads 2 are longer than conventional ones, and therefore, during the outer bonding of the semiconductor chip 1, the inner bonding portion between the semiconductor chip 1 and the finger leads 2 is shortened due to the reflow caused by this heat. There is no need to worry about the connection coming loose.
第６図は、第４図で示したアウターボンデイン
グ直前の状態の半導体チツプを加工した状態を示
す図で、フオーミングにより成形した状態を示
す。このフオーミングの加工は例えばアウターボ
ンデイングの直前に図示しないフイルムキヤリア
から打ち抜く時に行え、しかも、終端フイルム３
ｂの端部ｃを利用し、ここを基準にフオーミング
することが出来るのでやり易く、均一なものが得
られる。従つて、ボンデイング加工の前に終端フ
イルム３ｂを基準として、半導体チツプ１と中間
フイルム３ａとが基板４より浮いた状態でしかも
充分な空間を介して取付けることができる。さら
に、基準となる終端フイルム３ｂの部分は基板４
の表面と平行である。これにより、終端フイルム
はボンデイングツールとも平行となり、アウター
ボンデイング時、ボンデイングツールとフインガ
ー２ａとが接触する際に位置ずれの発生を防止す
ることができる。従つて、ボンデイングが容易に
できるようになり、しかも、ボンデイング接続の
信頼性が向上し、製品歩留りの向上につながる。 FIG. 6 is a diagram showing a processed state of the semiconductor chip immediately before outer bonding shown in FIG. 4, and shows a state in which it has been formed by forming. This forming process can be carried out, for example, when punching out a film carrier (not shown) immediately before outer bonding, and it is also possible to
Forming can be done using the end c of b as a reference, so it is easy to form and a uniform product can be obtained. Therefore, before the bonding process, the semiconductor chip 1 and the intermediate film 3a can be attached with the terminal film 3b as a reference while floating above the substrate 4 and with a sufficient space therebetween. Furthermore, the portion of the terminal film 3b that serves as a reference is the substrate 4.
is parallel to the surface of Thereby, the terminal film is also parallel to the bonding tool, and it is possible to prevent positional deviation from occurring when the bonding tool and the finger 2a come into contact during outer bonding. Therefore, bonding can be easily performed, and the reliability of the bonding connection is improved, leading to an improvement in product yield.
なお、前記説明した２段設置のポリイミドフイ
ルムを、１段設置で巾の広いポリイミドフイルム
で構成することも考えられるが、この場合には、
その面積は広くなり、したがつて、その後の脱泡
技術によるコーテイング加工の際、その材質が軟
材であることから変形し、基板４上の配線パター
ンと面接触し、シヨートする恐れがあること、
又、フオーミングにおいては、第７図、第８図の
様になり、第７図の場合はボンデイング部のフイ
ンガーとボンデイングツールが平行にならないこ
と、第８図の場合は特にピツチ変換を行つたポリ
イミドフイルムと基板とが接触するという問題が
有り、得策ではない。 Note that it is also possible to configure the above-described two-stage polyimide film with a single-stage wide polyimide film, but in this case,
The area becomes larger, and therefore, during the subsequent coating process using degassing technology, since the material is a soft material, it may deform, come into surface contact with the wiring pattern on the board 4, and may be shot. ,
In addition, in forming, the results are as shown in Figures 7 and 8. In the case of Figure 7, the fingers of the bonding part and the bonding tool are not parallel, and in the case of Figure 8, the polyimide that has undergone pitch conversion is There is a problem that the film and the substrate come into contact with each other, which is not a good idea.
（発明の効果）
以上、詳細に述べて来たように本発明によれ
ば、ポリイミドフイルムを２段設置してフインガ
ーリードを形成したので、該フインガーリードと
基板との接触がなくなりシヨートする危険性がな
く、したがつて、基板上の半導体チツプの実装部
分に配線パターンの形成や実現出来、高密度実装
が行える。又、フインガーリードのフオーミング
も行い易くなり、したがつて、ボンデイングの際
の位置ずれが押えられ、得られる接続の信頼性が
向上し、更には、必要に応じて２段設置のポリイ
ミドフイルムを利用してフインガーリードのパタ
ーンチツプ後を変化させて形成出来る等、優れた
効果が期待出来る。(Effects of the Invention) As described above in detail, according to the present invention, since the finger leads are formed by installing two layers of polyimide films, there is no contact between the finger leads and the substrate. There is no danger, and therefore wiring patterns can be formed and realized on the mounting area of the semiconductor chip on the board, and high-density mounting can be performed. In addition, forming the finger leads becomes easier, which prevents misalignment during bonding and improves the reliability of the resulting connection.Furthermore, it is possible to use two-stage polyimide film as needed. By using this method, excellent effects can be expected, such as being able to form finger leads by changing the pattern behind the chip.
第１図は従来の半導体チツプの状態を示す図、
第２図、第３図は各々第１図で示した半導体チツ
プを基板に実装した状態を示す図、第４図は本発
明を適用した半導体チツプの状態の一例を示す
図、第５図は第４図で示した半導体チツプを基板
に実装した状態を示す図、第６図は半導体チツプ
の他の状態を示す図、第７図、第８図はフオーミ
ングを説明する図である。
１…半導体チツプ、２…フインガーリード、２
ａ…フインガー、３ａ…中間フイルム、３ｂ…終
端フイルム、４…基板、４ａ…接続パターン、４
a′…配線パターン。
Figure 1 is a diagram showing the state of a conventional semiconductor chip.
2 and 3 are views showing the state in which the semiconductor chip shown in FIG. 1 is mounted on a substrate, FIG. 4 is a view showing an example of the state of the semiconductor chip to which the present invention is applied, and FIG. FIG. 4 is a diagram showing a state in which the semiconductor chip shown in FIG. 4 is mounted on a substrate, FIG. 6 is a diagram showing another state of the semiconductor chip, and FIGS. 7 and 8 are diagrams for explaining forming. 1...Semiconductor chip, 2...Finger lead, 2
a...Finger, 3a...Intermediate film, 3b...Terminal film, 4...Substrate, 4a...Connection pattern, 4
a′...Wiring pattern.
Claims (1)
に半導体チツプを組込むフイルムキヤリア方式を
用いた半導体チツプの実装方法において、 該半導体チツプのフインガーリードを、該フイ
ンガーリードと直角方向に設置した中間フイルム
及び終端フイルム上に形成し、 前記フインガーリードの前記中間フイルムと前
記終端フイルムとの間に立上がり部を形成し、 前記終端フイルムより外側で前記フインガーリ
ードのボンデイングを行うことを特徴とする半導
体チツプの実装方法。 ２ 前記中間フイルムではフインガーリードのパ
ターン及びピツチを変化させ、前記終端フイルム
ではフインガーリードのピツチを基板上のボンデ
イングピツチと同一ピツチに変化させてフインガ
ーリードを形成したことを特徴とする特許請求の
範囲第１項記載の半導体チツプの実装方法。[Claims] 1. A semiconductor chip mounting method using a film carrier method in which a semiconductor chip is assembled into a device hole provided in a tape-like film, wherein the finger leads of the semiconductor chip are mounted in a direction perpendicular to the finger leads. forming a rising portion between the intermediate film and the end film of the finger lead, and bonding the finger lead outside the end film; A semiconductor chip mounting method characterized by: 2. A patent characterized in that finger leads are formed by changing the pattern and pitch of the finger leads in the intermediate film, and changing the pitch of the finger leads in the terminal film to be the same pitch as the bonding pitch on the substrate. A method for mounting a semiconductor chip according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58157886A JPS6050932A (en) | 1983-08-31 | 1983-08-31 | Mounting method for semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58157886A JPS6050932A (en) | 1983-08-31 | 1983-08-31 | Mounting method for semiconductor chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6050932A JPS6050932A (en) | 1985-03-22 |
| JPH0330987B2 true JPH0330987B2 (en) | 1991-05-01 |
Family
ID=15659563
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58157886A Granted JPS6050932A (en) | 1983-08-31 | 1983-08-31 | Mounting method for semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6050932A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0719943B2 (en) * | 1986-07-04 | 1995-03-06 | 日本電気株式会社 | Electronic component mounting structure |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5688347A (en) * | 1979-12-20 | 1981-07-17 | Nec Corp | Semiconductor device |
-
1983
- 1983-08-31 JP JP58157886A patent/JPS6050932A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5688347A (en) * | 1979-12-20 | 1981-07-17 | Nec Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6050932A (en) | 1985-03-22 |
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