JP3824076B2 - Film carrier tape manufacturing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a film carrier tape.
[0002]
[Background]
In pursuit of high-density mounting of semiconductor devices, bare chip mounting is ideal. However, quality assurance and handling are difficult in the bare chip state. Therefore, CSP (Chip Scale / Size Package) has been developed as a package in which a bare chip is packaged, but the package size is close to the size of the bare chip.
[0003]
Among the CSP type semiconductor devices developed in various forms, as one form, a flexible substrate is provided on the active surface side of the semiconductor chip, and a plurality of external electrodes are formed on the flexible substrate. There is something. In this CSP type semiconductor device, the external electrode is provided in the area of the semiconductor chip. Therefore, for example, there is no so-called “outer lead” in which a lead protrudes from the side surface of the package body, such as QFP (Quad Flat Package) and TCP (Tape Carrier Package).
[0004]
Further, in a CSP type semiconductor device using a flexible substrate, as described in, for example, International Publication WO95 / 08856, a resin is injected between the active surface of the semiconductor chip and the flexible substrate, thereby causing thermal stress. It is also known to absorb water. If all the joints with the electrodes of the semiconductor chip are covered with this resin, corrosion of the electrodes can be prevented.
[0005]
Furthermore, when a semiconductor chip is mounted on a flexible substrate, if a film carrier tape is used, handling becomes easier, and mass productivity is excellent. In the system using a film carrier tape, each semiconductor device is cut from the film carrier after resin sealing of the semiconductor chip.
[0006]
Here, the wiring formed on the film carrier tape is gold-plated. Gold plating is performed by an electroplating (also referred to as “electrolytic plating”) method. In the electroplating method, it is general that all the wiring is made conductive and the wiring is drawn to the outside of the mounting area with the semiconductor chip. The drawn wiring was used as an electrode for electroplating. Conventionally, there is an outer lead, and the outer lead is pulled out as it is, and used as a wiring for electroplating. In addition, when an existing flexible substrate is used, a plating lead for electroplating is required. Usually, a plating lead is provided directly connected to a connection lead, and a TAB (Tape Automated Bonding) substrate used for a conventional TCP is known for this structure.
[0007]
However, when this conventional TAB substrate is used as it is and applied to a CSP type semiconductor device, each connection lead is directly connected to each plating lead, so that it is usually at a place called an outer lead. When cut, each lead end face protrudes from the package end face, and the lead end face is always exposed. In the CSP type semiconductor device, the distance between the chip outer shape and the package outer shape is very narrowed by making the package outer shape close to the chip size. Therefore, although it is packaged to protect the semiconductor chip, it is necessary to work to improve reliability including the environment surrounding the semiconductor chip as compared with the conventional package. In particular, when the above-described conventional structure is used as it is in a CSP type semiconductor device, the distance from the lead cut surface to the electrode of the semiconductor chip is very short, and the lead end is exposed without being covered. Because of this structure, the corrosion of the electrode is likely to proceed through the lead. Also, as the pitch between adjacent leads is further narrowed, the lead may be short-circuited due to, for example, conductive foreign matter existing on the exposed cut surface, and the function may be impaired. .
[0008]
On the other hand, this problem can be avoided by cutting individual semiconductor devices from the film carrier tape and then injecting resin. In this case, however, the separated semiconductor devices must be handled individually, and the advantages of the system using the film carrier tape cannot be utilized.
[0009]
The present invention solves the above-described problems, and an object thereof is to provide a film carrier tape manufacturing method for obtaining a semiconductor device having a package size close to the chip size.
[0010]
[Means for Solving the Problems]
The method for producing a film carrier tape according to the present invention comprises:
A plurality of connection leads formed in a region to be sealed and bonded to the electrodes of the semiconductor chip and the external electrodes, and at least one plating connected to the connection leads and formed outside the sealing region The method includes a step of forming a conductive pattern on a film, having a lead and a plating electrode to which the plating lead is connected, in a state where all of the leads are conductive.
[0011]
Alternatively, the manufacturing method of the film carrier tape according to the present invention,
Forming a lead hole in the film;
Providing a metal foil on a region including the lead hole of the film;
Forming a conductive pattern comprising a pad portion, a connection lead, a plating lead, a plating electrode and a connection portion from the metal foil;
A step of plating the conductive pattern through the plating electrode;
Processing the connection portion to form a wiring pattern;
including.
[0012]
Here, the step of forming the wiring pattern may be performed by punching the connection portion.
[0013]
Moreover, the number of steps can be reduced by punching a plurality of the connecting portions together.
[0014]
Or the said punching may be performed corresponding to each connection part.
[0015]
Each connecting portion may be punched out by a circular hole.
[0016]
Alternatively, the circular hole may have an elliptical shape, and the major axis direction of the elliptical shape may be directed in a direction substantially orthogonal to a side forming the outer periphery of the semiconductor device.
[0017]
Moreover, you may provide a protective film in the area | region except the area | region where the said plating process is performed in the said conductive pattern before the process of performing the said plating process.
[0018]
A resin may be used as the protective film.
[0019]
A solder resist may be used as the resin.
[0020]
The film carrier tape used in the resin-encapsulated semiconductor device according to the present invention is
A pad portion in which external electrodes are formed in a region to be resin-sealed;
A plurality of connection leads which are arranged in a region to be resin-sealed and connect each external electrode and each electrode of the semiconductor chip;
At least one plating lead formed outside the resin-sealed region;
A plurality of connection portions for electrically connecting any one of the connection leads and the plating lead;
At least one hole formed in the connection portion for achieving electrical insulation between the connection lead and the plating lead;
A plating electrode to which the plating lead is connected;
Have
The pad portion, the connection lead, the plating lead, the connection portion, and the plating electrode are electroplated.
[0021]
The hole may be a rectangular hole and may be formed across a plurality of the connection portions.
[0022]
Alternatively, a plurality of the holes are formed,
Each hole may be a circular or elliptical hole, and may be formed corresponding to each of the connecting portions.
[0023]
Alternatively, the hole may have an elliptical shape, and a major axis direction of the elliptical shape may be directed in a direction substantially orthogonal to a side forming the outer periphery of the semiconductor device.
[0024]
By forming the hole as described above, the end face of the connecting portion is exposed from the hole, and the exposed end face of the connecting portion is covered with resin sealing. Thereby, the corrosion from a connection part to a connection lead can be prevented.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0026]
1-7 is a figure explaining the manufacturing method of the semiconductor device which concerns on the reference example used as the premise of this embodiment from the manufacturing stage of a film carrier tape. In particular, in FIGS. 1 to 5, the manufacturing process of the film carrier tape is described. The processes of FIGS. 6 and 7 include the film carrier tape and the semiconductor chip manufactured in the processes of FIGS. 1 to 5. This is a subsequent process after bonding, and is not necessarily performed immediately (continuously) following the process of FIGS.
[0027]
First, as shown in FIG. 1, a film 10 serving as a base material is prepared. The film 10 is a tape (long) formed of a resin such as polyimide or polyester, and the width is determined according to the size of a semiconductor chip (not shown) to be mounted. The film 10 is suitably made of a material having electrical insulation and flexibility.
[0028]
As shown in FIG. 2, the sprocket hole 12 and the lead hole 14 are formed in the film 10 by using a well-known drilling technique such as punching, laser processing, or chemical etching. As shown in FIG. 6, the lead hole 14 is formed in a region corresponding to the electrode 42 of the semiconductor chip 40 to be mounted. That is, the lead hole 14 is formed for bonding the connection lead 24 and the electrode 42.
[0029]
Next, an adhesive is applied to the film 10, and a metal foil, for example, a copper foil 16 as an example of a member capable of electrical conduction, is applied while being pressed by a heating and pressing means such as a heat roller (not shown). wear. FIG. 3 shows a state in which the copper foil 16 is attached to the film 10.
[0030]
Then, a desired conductive pattern 20 is formed from the foil-like copper foil 16 as shown in FIG. 4 by performing wet etching.
[0031]
The conductive pattern 20 includes a pad portion 22, a connection lead 24, a plating lead 26, a plating electrode 28, and a connection portion 29. At the stage of the conductive pattern 20, all are in an electrically conductive state. The pad portion 22 is for forming external electrodes by providing bumps such as solder balls. Accordingly, the pad portion 22 has a flat surface when viewed in plan and has a predetermined area (usually wider than the connection lead 24). Note that the pad portion 22 itself may be formed in a convex shape and have a function as a bump in advance. Further, the pad portion 22 may remain in a land state as shown in the drawing even after the semiconductor device is manufactured. However, in this case, it is necessary to provide a joining member such as solder on the side of the member to be mounted (mounting substrate). When the semiconductor chip is mounted on the film carrier tape (see FIG. 7), the pad portion 22 is disposed inside the region of the semiconductor chip 40 and in the region sealed with the molding material 36.
[0032]
One end of the connection lead 24 is connected to a pad portion 22 for forming an external electrode, and electrical connection with the pad portion 22 is achieved. Note that the connection lead 24 is formed thinner than the pad portion 22. The connection lead 24 only needs to have a width sufficient to achieve good electrical continuity, and is inevitably thinner than the pad portion 22 in consideration of a narrow pitch. This applies not only to the connection lead 24 but also to the connection portion 29 on the extension of the connection lead 24. Further, the other end portion of the connection lead 24 passes (strides) the lead hole 14 as shown in FIG. The connection lead 24 is connected to the electrode 42 of the semiconductor chip 40 at a portion located in the lead hole 14. The connection leads 24 are arranged in a region of resin sealing with a molding material 36 described later (see FIG. 7), similarly to the pad portion 22. The connection lead 24 is electrically connected to the plating lead 26 via a connection portion 29 that connects a section from the side of the lead hole 14 on the plating lead 26 side to the plating lead 26. Here, the plating lead 26 is formed so as to be located outside the resin sealing region. That is, the connection portion 29 is formed from the connection lead 24 in the resin-sealed region to the plating lead 26 outside the resin-sealed region. Each plating lead 26 is formed in the short direction of the tape-like film 10 and is connected to the plating electrode 28. The plating electrode 28 is formed in the longitudinal direction of the tape-like film 10. Although not shown on both sides of the conductive pattern 20 shown in FIG. 4, a similar conductive pattern connected to the plating electrode 28 is continuously formed.
[0033]
Next, the entire conductive pattern 20 is plated with gold through the plating electrode 28 by an electroplating (electrolytic plating) method. The plating process may be a plating process with tin or solder in addition to gold plating. A known method may be used depending on the situation such as joining. Then, as shown in FIG. 5, at least a part of the connection portion 29 located between the connection lead 24 and the plating lead 26 (that is, between the side of the lead hole 14 on the side of the plating lead and the plating lead 26). By cutting, a wiring pattern (circuit pattern) 30 is formed from the conductive pattern 20 of FIG. A known technique can be used as a cutting method regardless of a mechanical method or a chemical method. Further, even if the corresponding portion to be cut is not completely punched out, for example, the connection lead 24 and the plating lead 26 are in an electrically non-conductive state, that is, only the connection lead 24 may have its end portion free. Only the pattern at the corresponding position) may be half-etched. In other words, the base film 10 does not necessarily have to be completely removed. Thus, a long film carrier tape 34 on which a predetermined circuit is formed is obtained. In the state in which the wiring pattern 30 is formed, the connection lead 24 including the wiring located between the lead hole 14 and the hole 32, that is, the side electrically connected to the pad part 22 in the connection part 29. . In addition, after the process of forming the wiring pattern 30, when the connection lead is simply used, the wiring located between the lead hole 14 and the hole 32 is also included.
[0034]
Note that the step of punching the connection portion 29 is performed after the plating process and before the bonding step (see FIG. 6) for the electrodes 42 of the semiconductor chip 40. In this example, the hole 32 is formed by punching out the connecting portion 29. The hole 32 is an elongated rectangular hole in the figure, but the shape is not limited to this. As shown in FIG. 7, one of the pair of long sides forming the hole 32 is located in the resin-sealed region, and the other is located outside the resin-sealed region. The end face of the punched connection portion 29 is flush with the position of the long side forming the hole 32, and the end portion is exposed inside the hole 32. The exposed end surface of the connection portion 29 is covered with resin. In short, the hole 32 is formed to cover the exposed end face of the connection portion 29 in addition to forming a desired circuit.
[0035]
Next, as shown in FIG. 6, the film carrier tape 34 is disposed above the semiconductor chip 40. More specifically, a portion corresponding to the flexible substrate in the film carrier tape is aligned above the semiconductor chip 40. Here, when the semiconductor device is finally separated from the film carrier tape 34 and becomes a semiconductor device piece, the portion remaining as the substrate corresponds to the flexible substrate.
[0036]
The electrode 42 of the semiconductor chip 40 is disposed so as to face the lead hole 14 of the film carrier tape 34. The appropriate size of the semiconductor chip to be used is from the one where the end of the semiconductor chip is located beyond the side forming the inner side of the lead hole as shown in the figure to the side of the hole 32 on the lead hole 14 side. If it is of the size, the size does not matter. Further, a predetermined gap is formed between the semiconductor chip 40 and the film carrier tape 34. At this time, positioning is performed so that the connection lead 24 is disposed on the electrode 42 of the semiconductor chip 40. Then, the plurality of electrodes 42 and the plurality of connection leads 24 are bonded together or one by one. For bonding, a bump is preferably formed on either the electrode 42 or the connection lead 24.
[0037]
In addition, when the semiconductor chip 40 is arrange | positioned at the film carrier tape 34, the formation position of the wiring pattern 30 in this reference example is provided in the surface on the opposite side to the surface where the semiconductor chip of a film opposes. Therefore, it is preferable to insulate and protect the surface of the wiring pattern 30 by applying a resin such as a solder resist. In addition, it is also possible to make it cover previously with the said resin except the part which wants to electroplate. Here, the portion to be electroplated specifically refers to a connection lead, a land or the like. In this way, plating is not applied to unnecessary portions, so that waste of the plating material used for the plating process can be eliminated. Alternatively, if the film carrier tape 34 is disposed with the wiring pattern 30 facing the semiconductor chip 40, the application of solder resist or the like can be omitted.
[0038]
Next, as shown in FIG. 7, the semiconductor chip 40 is sealed with a molding material. Reference numeral 36 denotes a region where the molding material is located. 8 is a cross-sectional view taken along line VIII-VIII in FIG.
[0039]
Specifically, the molding material 36 is injected from the lead hole 14 into the gap between the semiconductor chip 40 and the film carrier tape 34. The molding material 36 covers the electrodes 42 of the semiconductor chip 40.
[0040]
Further, the molding material 36 is filled so as to cover the end surface 29 a of the connection portion 29 (that is, the end portion of the connection lead) whose end is exposed at the hole 32 of the film carrier tape 34. By doing so, the end surface 29a (the end portion of the connection lead) of the connection portion 29 connected to the electrode 42 of the semiconductor chip 40 is covered with the resin so as not to be exposed. Accordingly, corrosion from the connection portion 29 side to the connection lead 24 and further to the electrode 42 of the semiconductor chip 40 is prevented and insulation is achieved, so that the reliability of the semiconductor device is improved.
[0041]
Thus, when sealing with the molding material 36 is completed, the film carrier tape 34 is separated from the base film outside the region where the molding material 36 is located. In the case of separation, die cutting is performed collectively, and the film carrier tape 34 portion (that is, the flexible substrate portion) used for the package is punched out from the base of the film carrier tape 34. Regarding the punching position, for example, if the cutting position is within the hole 32 region and outside the region sealed with resin, the wiring pattern routing direction (longitudinal direction of the film) has already been processed, There is no external addition during the punching process.
[0042]
On the other hand, it is also possible to punch out at a position outside the hole 32 and not in the hole. Thus, by punching out the holes 32 so as not to be cut out, the final shape of the semiconductor device has linearity. In this case, there is an advantage that the outer shape of the semiconductor device can be easily recognized in the subsequent steps.
[0043]
Next, FIG.9 and FIG.10 is a figure which shows embodiment (modification of the said reference example) of this invention, and respond | corresponds to the elements on larger scale of FIG.
[0044]
In the film carrier tape 50 shown in FIG. 9, each connection portion 52 is punched out by a circular hole 54 and cut from the plating lead 56. That is, the circular hole has a diameter wider than the width of the connecting portion 52. The process of punching out the connection portion 52 is performed after the plating process and before the bonding process for the electrodes of the semiconductor chip. The reason for selecting the circular shape is that the flowability and adhesion of the resin are taken into consideration.
[0045]
Then, resin sealing is performed up to the position of the alternate long and short dash line 58 so that the end surface of the connection portion 52 exposed from the circular hole 54 is covered with resin. Thereafter, final punching is performed at the position of the two-dot chain line 59 to obtain a semiconductor device. The ends of the connection leads connected to the electrodes of the semiconductor chip are completely covered with the resin, and the semiconductor device thus obtained also has the same effect as the reference example.
[0046]
Further, in the film carrier tape 60 shown in FIG. 10, each connection portion 62 is punched out by a long hole 64 and cut from the plating lead 66. It has a long hole, that is, an elliptical shape. Then, the resin is sealed up to the position of the alternate long and short dash line 68 so as to cover the end face of the connecting portion 62 exposed from the long hole 64. Thereafter, the final punching position is a position of a two-dot chain line 69 inside the elongated hole 64. That is, when the final punching is performed, the shape of the long hole 64 is cut out. Thus, a semiconductor device can be obtained. Note that the final punching positions 59 and 69 in FIGS. 9 and 10 are not limited to this. This point will be described later.
[0047]
In FIG. 10, the direction of the long diameter of the long hole is provided in a direction substantially orthogonal to the side forming the outer periphery of the package as shown in FIG. 10, and in this way, the interface of the connecting portion is compared with the example of FIG. Furthermore, it is located where it was drawn from the outer periphery of the package. Therefore, the corrosion prevention effect of the lead can be further enhanced by increasing the distance to contact with the outside air. Further, if the hole is made long, the contact area with the resin can be widened, and the adhesive strength between the resin and the substrate can be further increased. At this time, since the direction of the long diameter of the long hole is provided in a direction substantially orthogonal to the side forming the outer periphery of the package, the pitch interval between the adjacent connection leads can correspond to a narrow pitch. However, if the pitch restriction is somewhat loose, there is no need to worry about the direction of the long diameter of the long hole, and it may be provided in a direction substantially orthogonal to the side forming the outer periphery of the package in the same manner as described above. It may be provided in a direction (that is, a direction substantially parallel to a side forming the outer periphery of the package).
[0048]
In FIGS. 9 and 10, the resin sealing positions 58 and 68 are shifted from the final die-cutting (cutting) positions 59 and 69. More specifically, the resin sealing position when viewed as a package is shown. By providing the cutting (punching) position further outside the stop position, the final shape of the semiconductor device has linearity. In subsequent steps, the outer shape of the semiconductor device can be easily recognized. Moreover, it is because there is no worry of damaging a resin sealing part in a cutting process.
[0049]
On the other hand, the resin sealing position and the cutting (punching) position do not necessarily have to be shifted and may be the same. Moreover, you may cut | disconnect in the position which is outside the position of the resin in a hole, and is settled in a hole. Note that even if the punching position and the resin sealing position are the same, it is not necessary to punch out again into the shape in which the resin is drawn in the hole, and it is sufficient to punch out into the outermost straight shape of the resin sealing portion. In any case, the end of each connection part connected to each connection lead is provided with a hole (circular hole, long hole, etc.) that is drawn from the end of the substrate (film carrier tape). Therefore, the end of the connection part is kept covered with the resin.
[0050]
In the above embodiment, when performing the plating process, a known electroless plating method may be used in addition to the electrolytic plating. Further, the film carrier tape itself is not limited to a tape composed of three layers of a conductive pattern, an adhesive, and a film as in this example. For example, a two-layer tape from which the adhesive is removed from the above-described configuration may be used. Good.
[0051]
In each of the above embodiments, a chip having electrodes formed on two sides is used. Needless to say, the present invention can also be applied to a case where electrodes are provided on four sides. At that time, rectangular holes are provided in four directions of the tape.
[0052]
In the present example, the so-called fan-in type in which the external electrode is drawn inwardly of the semiconductor chip region has been described. However, the fan-in type and the reverse fan-out type can be applied. In this case, the fan-in type can be performed by using this example, and the fan-out type can be performed by using a conventional technique.
[0053]
FIG. 11 shows a circuit board 100 on which the semiconductor device 110 manufactured by applying the above embodiment is mounted. Although not shown in detail, the pad portion 22 of the semiconductor device 110 and a connection portion (for example, a land) formed on the circuit board 100 are electrically connected. As the connection member, for example, a well-known solder is used, and the connection is made by interposing between them (the pad portion of the semiconductor device 110 and the connection portion of the circuit board 100). As the connection member, in addition to solder, various connection means such as an anisotropic conductive adhesive can be used.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a method for manufacturing a semiconductor device according to a reference example.
FIG. 2 is a diagram illustrating a method for manufacturing a semiconductor device according to a reference example.
FIG. 3 is a diagram for explaining a method for manufacturing a semiconductor device according to a reference example;
FIG. 4 is a diagram for explaining a method for manufacturing a semiconductor device according to a reference example;
FIG. 5 is a diagram for explaining a method for manufacturing a semiconductor device according to a reference example;
FIG. 6 is a diagram for explaining a method for manufacturing a semiconductor device according to a reference example;
FIG. 7 is a diagram for explaining a method for manufacturing a semiconductor device according to a reference example;
FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG.
FIG. 9 is a diagram illustrating this embodiment.
FIG. 10 is a diagram illustrating this embodiment.
FIG. 11 is a diagram illustrating a circuit board on which a semiconductor device manufactured by applying the present embodiment is mounted.
[Explanation of symbols]
20 Conductive Pattern 24 Connection Lead 26 Plating Lead 28 Plating Electrode 29 Connection Part 30 Wiring Pattern 36 Mold Material 42 Electrode

Claims (6)

In the method for manufacturing a film carrier tape,
Forming a lead hole in the film;
Providing a metal foil on a region including the lead hole of the film;
Forming a conductive pattern including a plurality of connection leads connecting the pad portion, the plating lead, the plating electrode, and the pad portion and the plating lead from the metal foil;
A step of plating the conductive pattern through the plating electrode;
For each of the connection leads, a step of punching the connection lead;
A method for producing a film carrier tape comprising: In the manufacturing method of the film carrier tape of Claim 1,
Each connection lead is a method of manufacturing a film carrier tape that is punched by a circular hole. In the manufacturing method of the film carrier tape of Claim 2,
The method of manufacturing a film carrier tape, wherein the circular hole has an elliptical shape, and the direction of the major axis of the elliptical shape is oriented in a direction substantially orthogonal to a side forming the outer periphery of the semiconductor device. In the manufacturing method of the film carrier tape in any one of Claims 1 thru | or 3,
A method for producing a film carrier tape, wherein a protective film is provided in a region excluding a region where the plating process is performed in the conductive pattern before the step of performing the plating process. In the manufacturing method of the film carrier tape of Claim 4,
A method for producing a film carrier tape, wherein a resin is used as the protective film. In the manufacturing method of the film carrier tape of Claim 5,
A method for producing a film carrier tape, wherein a solder resist is used as the resin.

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