JPH03257561A - Data processor - Google Patents

Abstract

PURPOSE:To improve the data transfer ability in a system by outputting simultaneously the bus using request signals to both a local bus serving as an I/O bus and a system bus and acquiring the bus using grant signals from both buses in a DMA transfer state. CONSTITUTION:The switch control means 101 and 102 switch the switch means 103 and 104 to a 2nd circuit from a 1st circuit with a prescribed instruction. Thus the bus using request signals are transmitted to a system bus control means 4 and a local bus control means 5 via a DMA controller 6. The local bus using grant signal received from the means 5 is sent to the controller 6. Then the memory access signal received from the controller 6 is sent to the means 5. Under such conditions, a local bus is available. Meanwhile the bus using grant signal received from the means 4 is sent to the means 5. Thus the system buses 10 and 11 are available. In such a constitution, the data transfer ability is improved in a system.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data processing device in which a CPU and an input/output device for DMA transfer are respectively connected to a system node via different local buses. This relates to speeding up DMA transfer.

[Prior Art] FIG. 4 is a block diagram showing an example of the configuration of a conventional data processing device of this type. In the figure, (1) is cpU, (
2) is a storage device (hereinafter referred to as MEM), (3) and (5)
) is a control unit that controls the system bus interface (hereinafter referred to as SBI), (4) is a system bus control unit (hereinafter referred to as SBC), (6) is a DMA control unit (hereinafter referred to as DMAC), and (7> is an input/output unit). device (hereinafter referred to as I10).

(8) is the address bus (hereinafter referred to as L-ADH) of the local bus between CPU (1) and MEM (2), (9> is the address bus between CPU (1) and MEM (2)). (10) is the data bus (hereinafter referred to as L-DATA) of the local bus between
(hereinafter referred to as 5-ADH), (11) is a data bus (hereinafter referred to as 5-DATA) of the system bus. (12
> is the address bus of the I10 bus (hereinafter referred to as 1-ADR) controlled by SBI (5), (18)
is the data bus (hereinafter referred to as I-DATA) of the I10 bus.

(14) is a DMA request signal (hereinafter referred to as DREQ signal) from I/O (7), (15) is a DMA C
(6) is the DMA permission signal (hereinafter referred to as DACK signal). (16) is the I10 bus use request signal (hereinafter referred to as HREQ signal) from DMAC (8), (17
) is the I10 bus use permission signal (
(hereinafter referred to as the HACK signal). (1B) is S B
System bus use request signal (hereinafter referred to as BR) from I (5)
(19) is the system bus use permission signal (hereinafter referred to as BG double signal) from S B C (4).
20) is a memory access signal (hereinafter referred to as MEMRD/WR signal) during DMA transfer from DMA C (8).

Figure 5 shows l10(7) and M
12 is a timing chart showing an operation when data is transferred to and from EM(2>).

I/O (7) and M E by D M A C (6)
When transferring data between M (2), first
10 (7) turns on the DREQ signal (14). D.R.E.
The DMAC (6) that received the Q signal (14) sends SBI
(5), outputs the HREQ signal (16>), and
S B I (5) which received the Q signal (1B) is D M
Return HACK signal (17) to AC (6). DM
Upon receiving the HACK signal (17), AC (8) outputs a DACK signal (15) to I/O (7), and further outputs MEMRD/W to SBI (5).
While outputting the R signal (20), 1- A DH (
12) Outputs the memory address.

When the HACK signal (17) is transmitted to the DMAC (6), the I-ADH (12) and I-DA of the I10 bus
This means that the right to use T A (13) has been given to DMAC (6).

S B I ( which received MEMRD/WR signal (20)
5) is the first time here to convert the BR multiplied signal 1B) to S B C (
4) Output. When S B C (4) receives the BR double signal 18〉, it sends the BG double signal 19) to S B I (5) if there is no other system bus in use.
Output.

Upon receiving the BG multiplied signal 19), SBI (5) outputs the memory address outputted to ■-ADH (12) to S-ADH (to). This makes it possible to access MEM (2) by DMA transfer.

As is clear from the above explanation, a data processing device with a system bus has the following characteristics.

(a) CPU (1) and I/O (7) are not connected to the same bus, so I/O (7) is connected to DM
CPU (1) can operate even during A transfer.

(b) Since multiple 5BIs (3) and (5) can be connected to the system bus, each 110 can be connected to a separate bus, and when performing multitasking, multiple It is possible to operate two Ilo at the same time, which is very effective.

[Problems to be Solved by the Invention] However, in the data processing device described above, when only a single I/O (7) operates, the DMAC (6)
receives permission to use the bus, that is, the HACK signal (17)
There shouldn't be any problem if you send the memory address to the system bus and transfer the data at the moment you receive it.
In a conventional data processing device, before sending the memory address of I-ADH (12) to 5-ADH (10), BR
It is necessary to exchange the double signal 18> and the BG double signal 19), and an extra time T (see FIG. 5) is required for data transfer.

This means that, from the perspective of the entire system, an extra time T is required for each data transfer, and as the amount of data transferred increases, the transfer capacity of the system deteriorates.

The present invention eliminates the above extra time T and achieves high speed and MA.
An object of the present invention is to provide a data processing device that enables data transfer.

[Means for Solving the Problems] A data processing device according to the present invention has a CPU and an input/output device that performs DMA transfer by a DMA control device, each connected to a system bus via different local buses, and further includes: A storage device is connected to the system bus, and the input/output device and the storage device are mutually accessed by controlling the system bus control means that controls the system bus and the local bus control means that controls the local bus of the system bus and the input/output device. It has the following switching means and switching control means.

The switching means includes a first circuit that sends a bus use request signal from the DMA control device to the local bus control means, and a second circuit that sends a bus use request signal to both the system bus control means and the local bus control means. and switches to either the first circuit or the second circuit. Also,
The switching control means switches the switching means from the first circuit to the second circuit based on a predetermined command.

[Function] In the present invention, when a predetermined command is received, the switching control means switches the switching means from the first circuit to the second circuit. Therefore, the bus use request signal from the DMA control device is sent to both the system bus control means and the local bus control means, and the local bus use permission signal from the local bus control means is sent to the DMA control device.
A memory access signal from the A control device is sent to the local bus control means. In this state, the local bus becomes usable. Further, a bus use permission signal from the system bus control means is sent to the local bus control means, and in this state the system bus becomes usable.

In this way, the local bus and the system bus are available almost simultaneously, allowing access to the storage device from the input/output device, for example.

[Embodiment] FIG. 1 is a block diagram showing the configuration of a data processing device according to an embodiment of the present invention. In the figure, (1) to (20
) is exactly the same as shown in FIG. (
25) is a switching circuit section, and (18a) is a switching circuit section (
HRE for S B I (5) after passing through 25)
The Q signal (18a) is a BR multiplied signal for the S B C (4) after passing through the switching circuit section (25).The S B I (5) above constitutes the local bus control means of the present invention. ing.

FIG. 2 is a circuit configuration diagram of the switching circuit section (25).

In the figure, (101) is an instruction decoding unit that decodes instructions from the CPU (1), and in the first stage of the program that performs MDA transfer, the switching circuit unit (25)
Decode the given instruction to enable it.

(102) is an instruction latch section, (10B) is an AND circuit, and (104) is an OR circuit. (110) is a switching valid command signal, 011) is a switching invalid command signal, (112)
) is a switching ON signal. Note that the instruction decoding unit (10
1) and the instruction latch unit (102) constitute the switching control means of the present invention, and the portion surrounded by a broken line including the AND circuit (1 (1B) and the OR circuit 004) constitutes the switching means of the present invention. It consists of

Next, the operation will be explained. First, a command to enable the switching circuit section (25) is sent from the CPU (1) to the system bus (10).
), <11) to the instruction decoding unit (101), the instruction decoding unit (101) decodes the instruction, and turns on the switching valid instruction signal (110).

When the switching enable command signal (110) is turned ON, it is transmitted to the command latch section (lQ2) and latched, the switching ON signal (112) is turned ON, and the AND circuit (103) is enabled.

FIG. 3 is a timing chart showing the operation during DAM transfer, and the operation will be explained below with reference to this figure.

As mentioned above, the AND circuit (103) of the switching circuit section (25)
) is enabled, in Figure 1 I /
When O(7) outputs the DREQ signal (14), D M
A C (6) switches the HREQ signal (16) to the switching circuit (2
Output to 5>. In FIG. 2, the HREQ signal (16
) is manually operated, the AND circuit (10
3) is turned ON, and furthermore, the BR multiplied signal 18a) obtained via the OR circuit (104) is turned ON. B.R.
The double signal 18a) is transmitted to S B C (4), and
The HREQ signal (16) is directly converted to the HREQ signal (lea
) and is transmitted to SBI (5).

In this way, the bus use request signal is simultaneously transmitted to S B C (4) and S B I (5), respectively, and
BG double signal 19 from C (4>) is S B I (5)
and the HACK signal (
17) is transmitted to DMAC (6).

Now, returning to Figure 1, the HACK signal (17> is DM
D M A C (
8) is allowed to perform DMA transfer, and ■10(7
), outputs the DACK signal (15>), and further outputs the S
MEMRD/WR signal (20〉) for B I (5)
Output. When the MEMRD/WR signal (20) is manually input, SBI (5) has already input the BG double signal 19) indicating permission to use the system bus. ) on I-A
The memory address of DH (12) is output. Then, the data of I/O (7) is transferred to I-D of local bus.
ATA (13) and system bus S-D AT
It is transferred to M E M (2) via A (11).

As is clear from the timing chart in Figure 3, I
/ DREQ signal from O(7) (14> ON to M
In the time 't' until the EMRD/WR signal (20) turns ON, it becomes possible to output the address of the local bus I-ADH (12) onto the system bus S-ADH (10), The time T in FIG. 5 can be omitted, and the time until the DMA transfer starts is shortened.

If the switching circuit section (25) is not used, the CPU section (1
) from the switching circuit unit (25) is decoded by the instruction decoding unit (101), and a switching invalidation instruction signal (
ill). The instruction latch unit (102) is cleared by the switching invalidation command signal (ill), and the switching ON signal (H2) is turned OFF. Switching ON signal (112) is O
By becoming an FF, the AND circuit (103) becomes invalid, and the IREQ signal (te) from the DMAC (8) is no longer directly transmitted to the SBC (4), and the S BR multiplied signal 18 from B I (5)
) is outputted, it is outputted as the BR multiplied signal 18a).
The signal is transmitted to BC(4) and operates as shown in the timing chart of FIG.

[Effects of the Invention] As explained in detail above, according to the present invention, during DMA transfer, bus use request signals are simultaneously output to both the local bus as the I10 bus and the system bus, and bus use permission signals are issued from both. As a result, what used to take 10T's (see Figure 5) for the memory address to be output to the system bus after the I10 DMA transfer request has now been reduced to 't' time (see Figure 5). (see Figure 3), the transfer speed is increased by the time "T", thereby improving the data transfer capability of the system.

For example, when transferring a large amount of data such as a hard disk, or when one l10L is not working (for example, when transferring an HDD or CM to back up the memory contents)
(when writing to T, etc.), it is possible to shorten the transfer time.

In addition, when operating a plurality of Ilo, the switching means of the present invention is switched to the first circuit and the second circuit is disabled,
By having a configuration similar to conventional data processing equipment,
It can also be operated so as not to interfere with the operations of other Ilo's.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a data processing device according to an embodiment of the present invention, FIG. 2 is a circuit configuration diagram showing details of the switching circuit section of FIG. 1, and FIG. 3 is the device of FIG. 1. 4 is a block diagram showing the configuration of a conventional data processing device, and FIG. 5 is a timing chart showing the operation of the device shown in FIG. 4. In the figure, (2> is MEM, (4) is SBC, (3), (5) is SBI, (6) is DMAC, (7
) is Ilo, and (25) is a switching circuit section. t7) Block diagram of the switching circuit Fig. 2, t-1 power of the device of the invention, timing + mart Fig. 3

Claims (1)

[Claims] A CPU and an input/output device for DMA transfer by a DMA control device are respectively connected to a system bus via different local buses, and a storage device is further connected to the system bus, and the system Data processing controlled by a system bus control means that controls a bus and a local bus control means that controls a local bus of the system bus and the input/output device so that the input/output device and the storage device can access each other. In the apparatus, a first circuit that sends a bus use request signal from the DMA control device to the local bus control means, and a second circuit that sends the bus use request signal to both the system bus control means and the local bus control means. has a circuit, and the first
or the second circuit, and switching control means for switching the switching means from the first circuit to the second circuit based on a predetermined command. data processing equipment.