JPH0323940B2 - - Google Patents

Info

Publication number
JPH0323940B2
JPH0323940B2 JP60298705A JP29870585A JPH0323940B2 JP H0323940 B2 JPH0323940 B2 JP H0323940B2 JP 60298705 A JP60298705 A JP 60298705A JP 29870585 A JP29870585 A JP 29870585A JP H0323940 B2 JPH0323940 B2 JP H0323940B2
Authority
JP
Japan
Prior art keywords
interrupt
processor
data
bit
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60298705A
Other languages
English (en)
Japanese (ja)
Other versions
JPS62157961A (ja
Inventor
Mikio Yonekura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fanuc Corp
Original Assignee
Fanuc Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fanuc Corp filed Critical Fanuc Corp
Priority to JP29870585A priority Critical patent/JPS62157961A/ja
Publication of JPS62157961A publication Critical patent/JPS62157961A/ja
Publication of JPH0323940B2 publication Critical patent/JPH0323940B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)
JP29870585A 1985-12-30 1985-12-30 マルチプロセツサシステムの割込制御方法 Granted JPS62157961A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29870585A JPS62157961A (ja) 1985-12-30 1985-12-30 マルチプロセツサシステムの割込制御方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29870585A JPS62157961A (ja) 1985-12-30 1985-12-30 マルチプロセツサシステムの割込制御方法

Publications (2)

Publication Number Publication Date
JPS62157961A JPS62157961A (ja) 1987-07-13
JPH0323940B2 true JPH0323940B2 (enrdf_load_stackoverflow) 1991-04-02

Family

ID=17863215

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29870585A Granted JPS62157961A (ja) 1985-12-30 1985-12-30 マルチプロセツサシステムの割込制御方法

Country Status (1)

Country Link
JP (1) JPS62157961A (enrdf_load_stackoverflow)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FI884026L (fi) * 1987-09-03 1989-03-04 Honeywell Bull Mikroprocessors vektoravbrott.
JP2624817B2 (ja) * 1989-02-15 1997-06-25 株式会社日立製作所 通信アダプタ
US7849362B2 (en) 2005-12-09 2010-12-07 International Business Machines Corporation Method and system of coherent design verification of inter-cluster interactions
US7711534B2 (en) 2005-12-09 2010-05-04 International Business Machines Corporation Method and system of design verification
US9367493B2 (en) 2005-12-09 2016-06-14 Globalfoundries Inc. Method and system of communicating between peer processors in SoC environment

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58178468A (ja) * 1982-04-14 1983-10-19 Omron Tateisi Electronics Co デ−タ処理システムの割込方式

Also Published As

Publication number Publication date
JPS62157961A (ja) 1987-07-13

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