JPH0317143B2 - - Google Patents

Info

Publication number
JPH0317143B2
JPH0317143B2 JP59061524A JP6152484A JPH0317143B2 JP H0317143 B2 JPH0317143 B2 JP H0317143B2 JP 59061524 A JP59061524 A JP 59061524A JP 6152484 A JP6152484 A JP 6152484A JP H0317143 B2 JPH0317143 B2 JP H0317143B2
Authority
JP
Japan
Prior art keywords
buffer
read
data
storage device
main memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59061524A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60205647A (ja
Inventor
Yasushi Yokoyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP59061524A priority Critical patent/JPS60205647A/ja
Publication of JPS60205647A publication Critical patent/JPS60205647A/ja
Publication of JPH0317143B2 publication Critical patent/JPH0317143B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP59061524A 1984-03-29 1984-03-29 デ−タ処理装置 Granted JPS60205647A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59061524A JPS60205647A (ja) 1984-03-29 1984-03-29 デ−タ処理装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59061524A JPS60205647A (ja) 1984-03-29 1984-03-29 デ−タ処理装置

Publications (2)

Publication Number Publication Date
JPS60205647A JPS60205647A (ja) 1985-10-17
JPH0317143B2 true JPH0317143B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1991-03-07

Family

ID=13173568

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59061524A Granted JPS60205647A (ja) 1984-03-29 1984-03-29 デ−タ処理装置

Country Status (1)

Country Link
JP (1) JPS60205647A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5084837A (en) * 1988-01-22 1992-01-28 Sharp Kabushiki Kaisha Fifo buffer with folded data transmission path permitting selective bypass of storage
JP2595332B2 (ja) * 1988-11-02 1997-04-02 三菱電機株式会社 ネットワーク・システムのデータ転送方式

Also Published As

Publication number Publication date
JPS60205647A (ja) 1985-10-17

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term