JPH03166821A - 半導体集積回路装置 - Google Patents
半導体集積回路装置Info
- Publication number
- JPH03166821A JPH03166821A JP1306972A JP30697289A JPH03166821A JP H03166821 A JPH03166821 A JP H03166821A JP 1306972 A JP1306972 A JP 1306972A JP 30697289 A JP30697289 A JP 30697289A JP H03166821 A JPH03166821 A JP H03166821A
- Authority
- JP
- Japan
- Prior art keywords
- ecl
- circuit
- level
- output
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 238000006243 chemical reaction Methods 0.000 claims abstract description 45
- 238000000605 extraction Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 18
- 230000003321 amplification Effects 0.000 description 7
- 238000003199 nucleic acid amplification method Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 238000003491 array Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- DRSFVGQMPYTGJY-GNSLJVCWSA-N Deprodone propionate Chemical compound C1CC2=CC(=O)C=C[C@]2(C)[C@@H]2[C@@H]1[C@@H]1CC[C@@](C(C)=O)(OC(=O)CC)[C@@]1(C)C[C@@H]2O DRSFVGQMPYTGJY-GNSLJVCWSA-N 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11898—Input and output buffer/driver structures
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1306972A JPH03166821A (ja) | 1989-11-27 | 1989-11-27 | 半導体集積回路装置 |
EP19900122572 EP0430147A3 (en) | 1989-11-27 | 1990-11-26 | Semiconductor gate array device compatible with ecl signals and/or ttl signals |
KR1019900019167A KR910010873A (ko) | 1989-11-27 | 1990-11-26 | 반도체 집적회로장치 |
US07/618,691 US5132573A (en) | 1989-11-27 | 1990-11-27 | Semiconductor gate array device compatible with ecl signals and/or ttl signals |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1306972A JPH03166821A (ja) | 1989-11-27 | 1989-11-27 | 半導体集積回路装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03166821A true JPH03166821A (ja) | 1991-07-18 |
Family
ID=17963482
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1306972A Pending JPH03166821A (ja) | 1989-11-27 | 1989-11-27 | 半導体集積回路装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US5132573A (de) |
EP (1) | EP0430147A3 (de) |
JP (1) | JPH03166821A (de) |
KR (1) | KR910010873A (de) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07131330A (ja) * | 1993-11-02 | 1995-05-19 | Nec Corp | 半導体集積回路 |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0379121A (ja) * | 1989-08-23 | 1991-04-04 | Hitachi Ltd | 半導体集積回路装置 |
US5254887A (en) * | 1991-06-27 | 1993-10-19 | Nec Corporation | ECL to BiCMIS level converter |
JP2917626B2 (ja) * | 1991-11-20 | 1999-07-12 | 日本電気株式会社 | 半導体集積回路装置 |
JPH05191263A (ja) * | 1992-01-16 | 1993-07-30 | Nec Corp | 半導体回路 |
US5428305A (en) * | 1992-04-29 | 1995-06-27 | Hughes Aircraft Company | Differential logic level translator circuit with dual output logic levels selectable by power connector options |
US5343094A (en) * | 1993-01-13 | 1994-08-30 | National Semiconductor Corporation | Low noise logic amplifier with nondifferential to differential conversion |
US5970255A (en) | 1995-10-16 | 1999-10-19 | Altera Corporation | System for coupling programmable logic device to external circuitry which selects a logic standard and uses buffers to modify output and input signals accordingly |
US5920729A (en) * | 1996-04-30 | 1999-07-06 | Vtc Inc. | Apparatus for providing pair of complementary outputs with first and subcircuits to convert non-complementary and complementary inputs to first and second pair of complementary output |
IT1292096B1 (it) * | 1997-06-05 | 1999-01-25 | Sgs Thomson Microelectronics | Circuito convertitore da logica bipolare a logica cmos a elevata velocita' |
GB2343069B (en) * | 1998-06-30 | 2003-11-05 | Sgs Thomson Microelectronics | An on-chip higher-to-lower voltage input stage |
US6271679B1 (en) | 1999-03-24 | 2001-08-07 | Altera Corporation | I/O cell configuration for multiple I/O standards |
US6836151B1 (en) * | 1999-03-24 | 2004-12-28 | Altera Corporation | I/O cell configuration for multiple I/O standards |
US7705655B2 (en) * | 2006-09-18 | 2010-04-27 | Micrel, Inc. | Input buffer circuit |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5812346A (ja) * | 1981-07-15 | 1983-01-24 | Nec Corp | 半導体集積回路 |
JPS5961046A (ja) * | 1982-09-30 | 1984-04-07 | Fujitsu Ltd | 集積回路装置 |
US4527079A (en) * | 1983-11-01 | 1985-07-02 | Advanced Micro Devices, Inc. | Integrated circuit device accepting inputs and providing outputs at the levels of different logic families |
JPS6119226A (ja) * | 1984-07-05 | 1986-01-28 | Hitachi Ltd | レベル変換回路 |
US4670673A (en) * | 1985-02-19 | 1987-06-02 | Advanced Micro Devices, Inc. | Multilevel differential ECL/CML gate circuit |
US4636665A (en) * | 1985-12-02 | 1987-01-13 | Motorola, Inc. | BIMOS memory sense amplifier |
US4849659A (en) * | 1987-12-15 | 1989-07-18 | North American Philips Corporation, Signetics Division | Emitter-coupled logic circuit with three-state capability |
US4945265A (en) * | 1989-07-13 | 1990-07-31 | National Semiconductor Corporation | ECL/CML pseudo-rail circuit, cutoff driver circuit, and latch circuit |
-
1989
- 1989-11-27 JP JP1306972A patent/JPH03166821A/ja active Pending
-
1990
- 1990-11-26 KR KR1019900019167A patent/KR910010873A/ko not_active Application Discontinuation
- 1990-11-26 EP EP19900122572 patent/EP0430147A3/en not_active Withdrawn
- 1990-11-27 US US07/618,691 patent/US5132573A/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07131330A (ja) * | 1993-11-02 | 1995-05-19 | Nec Corp | 半導体集積回路 |
Also Published As
Publication number | Publication date |
---|---|
KR910010873A (ko) | 1991-06-29 |
US5132573A (en) | 1992-07-21 |
EP0430147A2 (de) | 1991-06-05 |
EP0430147A3 (en) | 1992-11-19 |
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