JPH03147333A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03147333A JPH03147333A JP28621589A JP28621589A JPH03147333A JP H03147333 A JPH03147333 A JP H03147333A JP 28621589 A JP28621589 A JP 28621589A JP 28621589 A JP28621589 A JP 28621589A JP H03147333 A JPH03147333 A JP H03147333A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- silicon layer
- type
- polycrystalline silicon
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 29
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 15
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 13
- 229910052785 arsenic Inorganic materials 0.000 abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 10
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052710 silicon Inorganic materials 0.000 abstract description 10
- 239000010703 silicon Substances 0.000 abstract description 10
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 5
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 abstract description 3
- 239000013078 crystal Substances 0.000 abstract description 3
- 229910001882 dioxygen Inorganic materials 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 abstract description 3
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 abstract description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- -1 arsenic ions Chemical class 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置に関し、特にバイポーラ型半導体
装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a bipolar semiconductor device.
第２図は従来のＮＰＮ）ランジスタの一例の断面図であ
る。FIG. 2 is a sectional view of an example of a conventional NPN transistor.
Ｐ型シリコン基板１にＮ型埋込層２を設け、エピタキシ
ャル法でＮ型層３を形成する。このＮ型層３はコレクタ
領域となる。Ｎ型層３にＰ型ベース領域４を形成し、表
面を酸化膜５で覆う。エミッタ領域を形成する部分を開
口する。ＣＶＤ法を用いて多結晶シリコン層１０を堆積
する。砒素イオン等を注入した後熱処理して砒素をベー
ス領域中に拡散せしめてＮ型エミッタ領域９を形成する
。An N-type buried layer 2 is provided on a P-type silicon substrate 1, and an N-type layer 3 is formed by an epitaxial method. This N-type layer 3 becomes a collector region. A P type base region 4 is formed in the N type layer 3, and the surface is covered with an oxide film 5. A portion that will form an emitter region is opened. A polycrystalline silicon layer 10 is deposited using the CVD method. After implanting arsenic ions and the like, heat treatment is performed to diffuse the arsenic into the base region to form an N-type emitter region 9.
上述した従来のバイポーラトランジスタの形成において
は、多結晶シリコン層１０中の砒素が多結晶シリコン層
１０の結晶粒界】１に沿って拡散するため、エミッタの
拡散が不均一に行われる。In the formation of the conventional bipolar transistor described above, arsenic in the polycrystalline silicon layer 10 diffuses along the grain boundaries 1 of the polycrystalline silicon layer 10, resulting in non-uniform emitter diffusion.
このため、トランジスタの集積度が上がるに従って、確
率的にエミッタ９とベース４の空乏層とベース４とコレ
クタ３の空乏層がぶつかってエミッタ・コレクタ間が短
絡するパンチスルー現象や、エミッタ拡散層が完全にコ
レクタとつながる突き抜は現象が発生し、高集積回路の
実現が歩留的に困難となるという問題がある。For this reason, as the degree of integration of transistors increases, the depletion layer of the emitter 9 and base 4 and the depletion layer of the base 4 and collector 3 collide with each other, resulting in a punch-through phenomenon in which the emitter and collector become short-circuited, and the emitter diffusion layer A punch-through that is completely connected to the collector causes a phenomenon, and there is a problem in that it becomes difficult to realize a highly integrated circuit in terms of yield.
本発明は、−導電型コレクタ領域内に形成された逆導電
型ベース領域と、該ベース領域内に形成された一導電型
エミッタ領域と、該エミッタ領域上に形成された一導電
型多結晶シリコン層のエミッタ電極とから成るバイポー
ラトランジスタを有する半導体装置において、前記多結
晶シリコン層が、相対的に薄い下層多結晶シリコン層と
該下層多結晶シリコン層上に形成された厚さ１〜１０ｎ
ｍの酸化膜または高酸素含有率の多結晶シリコン層と該
酸化膜または高酸素含有率の多結晶シリコン層の上に形
成された相対的に厚い上層多結晶シリコン層とから成る
ことを特徴とする。The present invention includes - a base region of opposite conductivity type formed in a collector region of conductivity type, an emitter region of one conductivity type formed in the base region, and a polycrystalline silicon of one conductivity type formed on the emitter region. In a semiconductor device having a bipolar transistor comprising a layer of an emitter electrode, the polycrystalline silicon layer has a relatively thin lower polycrystalline silicon layer and a layer having a thickness of 1 to 10 nm formed on the lower polycrystalline silicon layer.
m oxide film or a polycrystalline silicon layer with a high oxygen content, and a relatively thick upper polycrystalline silicon layer formed on the oxide film or the polycrystalline silicon layer with a high oxygen content. do.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）、（ｂ）は本発明の一実施例の製造方法を
説明するための工程順に示した断面図である。FIGS. 1(a) and 1(b) are sectional views showing the order of steps for explaining a manufacturing method according to an embodiment of the present invention.
まず、第１図（ａ）に示すように、Ｐ型シリコン基板１
にＮ型埋込層２を設け、エピタキシャル法でＮ型層３を
形成する。このＮ型層３はコレクタ領域となる。Ｎ型層
３にＰ型ベース領域４を形成し、表面を酸化膜５で覆う
、エミッタ領域を形成する部分を開口する。ＣＶＤ法を
用いて下層多結晶シリコン層６を約２０ｎｍ程度の厚さ
に堆積する。このように薄く堆積すると結晶粒径が大き
くならないという利点がある。First, as shown in FIG. 1(a), a P-type silicon substrate 1
An N-type buried layer 2 is provided on the substrate, and an N-type layer 3 is formed by an epitaxial method. This N-type layer 3 becomes a collector region. A P-type base region 4 is formed in the N-type layer 3, the surface of which is covered with an oxide film 5, and a portion where an emitter region will be formed is opened. A lower polycrystalline silicon layer 6 is deposited to a thickness of about 20 nm using the CVD method. This thin deposition has the advantage that the crystal grain size does not become large.
次に、ＣＶＤ装置内で酸素ガスを流すことによりシリコ
ン酸化ｐＡ７を１０ ｎ ｍ未満の厚さに形成する８次
に、酸素ガスを遮断し、再びＣＶＤ法により上層多結晶
シリコン層８を２０Ｏｒ＋ｍ程度の厚さに堆積する。ホ
トリソグラフィ技術を用いて選択エツチングして図示す
る形状にする。Next, silicon oxide pA 7 is formed to a thickness of less than 10 nm by flowing oxygen gas in the CVD apparatus.Next, the oxygen gas is cut off, and the upper polycrystalline silicon layer 8 is formed by CVD again to a thickness of about 20 Or+m. Deposited to a thickness of . Selective etching is performed using photolithography techniques into the shape shown.
次に、第１図（ｂ）に示すように、砒素イオンＡ ｓ、
”を上層多結晶シリコンＭ８に注入する。Next, as shown in FIG. 1(b), arsenic ion A s,
” is implanted into the upper layer polycrystalline silicon M8.
次に、９００°Ｃ程度で熱処理することにより、砒素を
ベース領域４内へ導入し、Ｎ型エミッタ領域９を形成す
るのであるが、本発明においては膜厚１０ｎｍ未溝のシ
リコン酸化膜７が存在するため、上層多結晶シリコン酸
化内の砒素は結晶粒界１１に沿って拡散するものの、上
層多結晶シリコンＮ８の下方に存在するシリコン酸化膜
７により砒素の拡散が阻止され、シリコン酸化膜７の上
部で砒素が蓄積される６その後、シリコン酸化膜７の中
を砒素がメルトスルーにより通過する。このため、砒素
の拡散が場所的に均一となる。その上、シリコン酸化膜
７の下の下層多結晶シリコン６の粒径が小さいため、ベ
ース領域４中へは砒素が均一・に拡散され、均一なＮ型
エミッタ領域９が形成される。Next, arsenic is introduced into the base region 4 by heat treatment at about 900°C to form an N-type emitter region 9. In the present invention, the ungrooved silicon oxide film 7 with a thickness of 10 nm is Therefore, arsenic in the upper polycrystalline silicon oxide diffuses along the grain boundaries 11, but the diffusion of arsenic is prevented by the silicon oxide film 7 existing below the upper polycrystalline silicon oxide, and the silicon oxide film 7 After that, arsenic is accumulated in the upper part of the silicon oxide film 7 and passes through the silicon oxide film 7 by melt-through. Therefore, the diffusion of arsenic becomes uniform in location. Furthermore, since the grain size of the lower polycrystalline silicon 6 under the silicon oxide film 7 is small, arsenic is uniformly diffused into the base region 4, and a uniform N-type emitter region 9 is formed.
上記実施例では、シリコン酸化ＷＡ７を形成したが、酸
化物になるに至らない高酸素含有率の多結晶シリコン層
であっても酸化物に近い効果が得られる。In the above embodiment, silicon oxide WA7 was formed, but even with a polycrystalline silicon layer with a high oxygen content that does not reach the level of oxide, effects similar to those of oxide can be obtained.
また、本実施例ではＮＰＮ）ランジスタの場合を説明し
たが、極性を逆にすればＰＮＰ トランジスタにも本発
明を適用できる。Furthermore, although the case of an NPN transistor has been described in this embodiment, the present invention can also be applied to a PNP transistor by reversing the polarity.
以上説明したように、本発明は、エミッタ形成用の多結
晶シリコン層の成長初期にシリコン酸化膜または酸素含
有率の高い層を形成し、単結晶と接する多結晶シリコン
層の粒径が大きくならないように抑制することにより、
単結晶シリコン層中に形成されたベース領域への不純物
の拡散を均一に行なわせて、均一なエミッタ領域を形成
することができるという効果がある。均一なエミッタは
、エミッタ・コレクタ間の短絡が発生しないため、高歩
留の集積度の高いバイポーラ集積回路を実現することが
可能となる。As explained above, the present invention forms a silicon oxide film or a layer with a high oxygen content at the early stage of growth of a polycrystalline silicon layer for forming an emitter, thereby preventing the grain size of the polycrystalline silicon layer in contact with the single crystal from increasing. By suppressing the
This has the effect of uniformly diffusing impurities into the base region formed in the single crystal silicon layer, thereby forming a uniform emitter region. Uniform emitters do not cause short circuits between the emitter and collector, making it possible to realize bipolar integrated circuits with high yield and high integration density.
第１図（ａ）、（ｂ）は本発明の一実施例の製遣方法を
説明するだめの工程順に示した断面図、第２「４は従来
のＮＰＮトランジスタの一例の断面図である。
１・・・Ｐ型シリコン基板、２・・・Ｎ型埋込層、３・
・・Ｎ型層、４・・・Ｐ型ベース領域、５・・・酸化膜
、６・・・１’−層多結晶シリコン層、７・・・シリコ
ン酸化膜、８・・・−４−層多結晶シリコン層、９・・
・Ｎ型エミッタ領域、１０・・・Ｎ型多結晶シリコン層
、１１・・結晶粒界、】２・・・バンチスル一部。FIGS. 1(a) and 1(b) are cross-sectional views showing the manufacturing method of an embodiment of the present invention in the order of steps, and FIG. 2(4) is a cross-sectional view of an example of a conventional NPN transistor. 1... P type silicon substrate, 2... N type buried layer, 3...
... N type layer, 4... P type base region, 5... oxide film, 6... 1'-layer polycrystalline silicon layer, 7... silicon oxide film, 8...-4- Layer polycrystalline silicon layer, 9...
- N-type emitter region, 10... N-type polycrystalline silicon layer, 11... Grain boundary, ]2... Part of bunchesle.
Claims (1)
領域と、該ベース領域内に形成された一導電型エミッタ
領域と、該エミッタ領域上に形成された一導電型多結晶
シリコン層のエミッタ電極とから成るバイポーラトラン
ジスタを有する半導体装置において、前記多結晶シリコ
ン層が、相対的に薄い下層多結晶シリコン層と該下層多
結晶シリコン層上に形成された厚さ１〜１０ｎｍの酸化
膜または高酸素含有率の多結晶シリコン層と該酸化膜ま
たは高酸素含有率の多結晶シリコン層の上に形成された
相対的に厚い上層多結晶シリコン層とから成ることを特
徴とする半導体装置。A base region of opposite conductivity type formed within a collector region of one conductivity type, an emitter region of one conductivity type formed within the base region, and an emitter electrode of a polycrystalline silicon layer of one conductivity type formed on the emitter region. In a semiconductor device having a bipolar transistor, the polycrystalline silicon layer includes a relatively thin lower polycrystalline silicon layer and a 1 to 10 nm thick oxide film or high oxygen film formed on the lower polycrystalline silicon layer. 1. A semiconductor device comprising a polycrystalline silicon layer having a high oxygen content and a relatively thick upper polycrystalline silicon layer formed on the oxide film or the polycrystalline silicon layer having a high oxygen content.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28621589A JPH03147333A (en) | 1989-11-02 | 1989-11-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28621589A JPH03147333A (en) | 1989-11-02 | 1989-11-02 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03147333A true JPH03147333A (en) | 1991-06-24 |
Family
ID=17701465
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28621589A Pending JPH03147333A (en) | 1989-11-02 | 1989-11-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03147333A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06232147A (en) * | 1992-08-19 | 1994-08-19 | Nec Corp | Semiconductor device and manufacture thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6191961A (en) * | 1984-10-12 | 1986-05-10 | Nec Corp | Manufacture of semiconductor device |
-
1989
- 1989-11-02 JP JP28621589A patent/JPH03147333A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6191961A (en) * | 1984-10-12 | 1986-05-10 | Nec Corp | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06232147A (en) * | 1992-08-19 | 1994-08-19 | Nec Corp | Semiconductor device and manufacture thereof |
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