JPS59138369A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain an I<2>L without the generation of the failure of collector-base withstand voltage by a method wherein a semiconductor layer containing an imurity of conductivity type different from that of a base region is placed on said region, and a collector region is formed by making the thickness of an insulation layer covering said layer larger in the side surface than in the upper surface, when the collector region is formed in the base region. CONSTITUTION:An N<+> buried region 2 is diffusion-formed in the surface layer part of a P type Si substrate 1, an N type epitaxial layer 3 is epitaxially grown over the entire surface including said region, and an N<+> type emitter region 4 reaching the region 2 is formed thereat. Next, thick field oxide films 5 are formed on both sides of the surface of the region 4 and on the other end of the layer 3, a P type injector region 6 and a P type common base region 7 are diffusion-formed in the layer 3 other than the region 4, and the clearance therebetween is covered with an oxide film 14. Thereafter, an As doped polycrystalline Si layer 8 is provided on the region 7 and surrounded by an insulation film. The impurity in the layer 8 is diffused by heat treatment, thus forming an N<+> type collector region 10 in the region 7; while, the layer 8 is not only surrounded by an oxide film 11 but provided with a nitride film, etc. by superposition further on the side surface.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device @VC having a base connection that is self-aligned to
ted Injection Logic) and its manufacturing method.

I2Lμ has an inverter transistor consisting of a so-called reverse structure vertical transistor in which the emitter and collector of a normal planar bipolar transistor are reversed, and a complementary injector transistor with the base of this transistor as the collector. There is.

Also, I21. It has a small logic amplitude, enables high-speed and low-power operation, and does not require element isolation, allowing for high integration, and is characterized by the ability to coexist on the same chip with conventional bipolar integrated circuits. .

As a method for speeding up l2L'i, refer to document IIII)
M Tech, Dig 1979 J Ic J-8
ub-nanosecond 8etf-atigne
d 12L/MTL C1rcuitsJ,
7 layers of heavily n-type doped polycrystalline silicon are formed in the collector region of L2L, making it possible to form a base contact hole and a collector region by self-alignment due to the difference in the thickness of the silicon oxide film, and further exposing the surface to the surface. An IL is shown in which the base region is covered with metal to lower the base resistance, enable miniaturization of the element, and enable a structure in which the emitter-base and collector-base junction area ratio approaches 't-11C. .

However, this I2L has many problems.

The conventional manufacturing method shown in FIG. 1' will be explained below.

First, p-type silicon substrate lvC high humidity n-type buried layer 2ft
After forming the n-type epitaxial layer 3, a high concentration n+ type diffusion region 4t is formed from its surface.

Emitter (a) 0th order silicon nitride film 1fr:
1OOOA is deposited, and a silicon oxide film 5 of approximately 1 μm is selectively formed with a hole in a portion (b). Injector area 6
After forming the base region 7t, a CVD silicon oxide film of 5000A is deposited on the entire surface of the arsenic-doped polycrystalline silicon layer 8.
! Deposit r5000A. This CVI) 5iU2 is etched and further Ic HF:HN(J3:CH
The entire arsenic-doped polycrystalline silicon layer 8 is selectively etched using a mixed solution of 3CO0H=1:3:8 (C). Next, a silicon oxide film 11 is formed at a low temperature (700 to 900°C) while forming a collector region 1O by full diffusion from arsenic-doped polycrystalline silicon 8.
At this time, the base 7 and the injector 6
A silicon oxide film 12 with a thickness of several tens of μA is formed on the top, and a silicon oxide film 12 with a thickness of 1000 to 200 μA is formed on the side surfaces of the arsenic-doped polycrystalline silicon 8.
The silicon oxide film 11 of A is formed (d) - This 1 The oxide film growth rate of the high concentration n1 type semiconductor layer 8 is 1 compared to the low allp type semiconductor layer 6.7 due to oxidation at a low temperature.
This is because it has a high oxide film growth rate. - The thin oxide film 12 on the injector 6 and base 7 is etched in a self-aligned manner to open all contact holes.

All metal electrodes 13 are formed (eJ.

However, this method has the following drawbacks.

In other words, the difference in the growth rate of silicon oxide films due to low-temperature oxidation, that is, the lower the temperature of the oxide film 11 grown by low-temperature oxidation of the high #degree rare semiconductor layer 8, the lower the concentration of the p-type semi-exclusive layer. Silicon oxide film 12 formed on 6 and 7
It is formed more thickly.

However, on the other hand, it is known that it cannot be used because the film quality is too dense and the etching speed with a p-hydrofluoric acid-based etching solution is too fast and the etchability is poor. This causes a short circuit between the base and collector.

An object of the present invention is to eliminate collector base breakdown voltage defects.

An object of the present invention is to provide a highly reliable semiconductor device fIt.

In the present invention, anisotropic etching is performed by covering the entire polycrystalline semiconductor with an insulating film, and by kneading, the insulating film on the side surfaces of the polycrystalline semiconductor becomes thicker than that on the top surface.

Embodiments of the present invention will be described in detail below with reference to one drawing.

First, a high concentration n1 type buried region 2 is provided in a p type semiconductor substrate l, an n type epitaxial layer 3 is formed thereon, and a high fA degree V type diffusion region 4 is formed from the surface of the shrimp layer to form an emitter. area (Fig. 2(a)). Next, a silicon nitride film with a thickness of 1000 to 1500 A is formed on the substrate surface, and a portion of the silicon nitride film is opened and selectively overlapped to form the oxide film 5. After removing the C nitride film, a CVI) oxide film 14't- is grown. , the injector lateral J'NP is removed leaving behind a space region, and the injector 6 and the inverter base region 7 are formed by ion implantation (FIG. 2(b)). Arsenic-doped polycrystalline silicon layer 8'k 3000-500 (I
A is deposited and selectively removed leaving the area that will become the collector (Figure 2 (C)), and the entire surface is heated to a low temperature (700 to 900°C).
) to oxidize.

At this time, the surfaces of the injector 6 and base 7 are approximately 312 mm.
11 grow each.

Next, D 8102 or plasma nitride film 15 is coated with D 8102 or plasma nitride film 15 for a length of 5000 to 10000 A @.
2(e)), vertical etching is performed using an anisotropic etching device such as reactive ion etching. As a result, the upper VC of the polysilicon layer 8 is 2000 to 250.
Oxide film 12 on the surfaces of injector 6 and base 7 while leaving 0A oxide film? Etching @, -10,000.

The side surface of polysilicon 8 (1ctxcVl) 8tu2 or plasma nitride film is 5000~100O for its thickness.
OA remains (Fig. 2(f)).

After this, if necessary, diffuse vcp type impurities over the entire surface.

Form an electrode (Fig. 2(g)).

As explained above, the polysilicon side surface vc is 0.5~
The oxide film on the base surface can be removed while leaving a 1.0μ oxide film, which prevents base-collector short circuits, which was a major problem in conventional manufacturing methods.In addition, the collector base is formed in a self-aligned manner. Because of this, it can be made extremely small in size, and has a remarkable effect on high integration.

Note that the present invention relates to another device having a polycrystalline semiconductor layer.

For example, silicon games? MO8) Can be similarly applied to transistors 0 In other words, a silicon gate MOS transistor has a polycrystalline silicon layer serving as a gate insulated from a substrate via a gate insulating film, and uses this polycrystalline silicon layer as a mask to connect the source.

Apertures are formed for the drain regions to form these regions, and source and drain electrode interconnections are formed. Form an rc oxide film, etc., and perform vertical etching using anisotropic ion etching.

By leaving the insulating film on the side surface vc of the polycrystalline silicon layer and removing the insulating film on part of the source and drain regions, short circuits between the source and drain electrodes and the polycrystalline silicon gate can be prevented.

[Brief explanation of drawings]

Fig. 1 (al to e) U is a process sectional view showing a conventional mounting method, and Fig. 2 (a) to (g)'rX is a process sectional view showing an embodiment of the present invention. 1 is a p type substrate, 2-shaped injector area, 1-type buried layer. 3-type pit axial layer, 4-type (vine area), 5μ field oxide film, 6-type injector area, 7-type injector area.
1'; [p-type common base region, 8 arsenic-doped polycrystalline silicon, 9μ CVI) oxide film klOHnlOHn collector region length 11μ oxide film on polycrystalline hp-type paste, 13μ electrode, 14μ oxide film,
15 indicates an oxide film or a plasma nitride film. Figure 1 Figure l Figure Z

Claims (1)

[Claims] 1. Among the insulating films selectively formed on the semiconductor substrate, which are superior to the polycrystalline semiconductor layer, the thickness on the side surface of the polycrystalline semiconductor layer is thicker than the thickness on the top surface of the polycrystalline semiconductor layer. A semiconductor device characterized by: 2. A step of selectively forming a polycrystalline semiconductor layer on a semiconductor substrate or via an insulating film, and
forming an insulating film on the semiconductor substrate;
etching the insulating film using anisotropic etching using ion etching so as to leave the insulating film on the side surfaces of the polycrystalline semiconductor layer and remove the insulating film on a portion of the semiconductor substrate; A large manufacturing method for a semiconductor device 1W characterized by the following.