JPS6191961A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6191961A JPS6191961A JP59213855A JP21385584A JPS6191961A JP S6191961 A JPS6191961 A JP S6191961A JP 59213855 A JP59213855 A JP 59213855A JP 21385584 A JP21385584 A JP 21385584A JP S6191961 A JPS6191961 A JP S6191961A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- oxide film
- polysilicon
- polysilicon layer
- implanted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 36
- 229920005591 polysilicon Polymers 0.000 claims abstract description 35
- 239000012535 impurity Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 18
- 238000010438 heat treatment Methods 0.000 claims abstract description 7
- 238000009792 diffusion process Methods 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 7
- 238000000605 extraction Methods 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 230000001590 oxidative effect Effects 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 2
- 239000010408 film Substances 0.000 abstract 6
- 239000010409 thin film Substances 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 238000002513 implantation Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000007127 saponification reaction Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 229910000859 α-Fe Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42304—Base electrodes for bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
- Fuel Cell (AREA)
Abstract
Description
【発明の詳細な説明】
（技術分野）
本発明は半導体装置の製造方法に関し、特にポリシリコ
ン層上からイオン注入して拡散層とポリシリコンの引き
出し電極を形成する工程を含む半導体装置の製造方法に
関するものである０（従来技術）
ポリシリコン層上からイオン注入して拡散層とポリシリ
コンの引き出し電極を形成したバイポーラ多結晶シリコ
ン集積回路の製造方法には文献” ＰＳＡ −Ａ ＮＥ
Ｗ Ａｐｐｒｏａｃｈ ｆｏｒ ＢｉｐｏｌａｒＬＳＩ
”ｉｎ ＩＥＥＥ Ｖｏｌ ５Ｃ−１３、Ｎｏ ５
０ｃｔ１９７８、ｐ６９３に示される様なＰＳＡ（Ｐｏ
ｌｙ−ｓｉｌｉｃｏｎ ５ｅｌｆ Ａｌｉｇｎ ）プロ
セスがあり、これを例に従来技術をＭ１図を参照して説
明する０まず第１図に示す様Ｋｐ型シリコンに板１１上
にＮ型エピタキシャル層１２を形成し、いわゆる退択鹸
化法を用いて酸化膜１３ａを形成し、イオン注入法号で
Ｐ型不純物層１４（ベース部）を形成する。しかる後ポ
リシリコンを減圧気相成長法寺でＭ層後阿度選択淑化法
を用いて酸化膜１３ｂを形成する。次いてポリシリコン
層１７を介してホトレジストをマスクにＮ型？４〆）度
不純物を工ばツタ部およびコレクタコンタクト部へイオ
ン注入法により例えばＡｓ（ヒ素）を注入し、しかる後
熱処理を行ないＮ型不純物層としてのエミッタ部１５と
コレクタコンタクト部１６を得る次いて金属配線電極と
しての例えばアルばニウムガスバッター父は蒸庸法によ
り波層されて後ホトレジスト、エッナング技術によりパ
ターン形成されて金属配線層１１３となり１１１図の従
来製法よりなる構造を得る。エミ、り部１５とコレクン
コンタクト部１６上刃のＮ型不純物が含まれるポリシリ
コン層は拡散層と前記金属配線電極間を接αする引き出
し電極としての役割を持ちアルミニウム等の金りが浸入
して浅いエミッタ（合部を破壊する′ことのない悸なバ
イヤー性を有することが必要であることを付記しＣおく
０
（従来製法での欠点）
しかし上記従来製法における構造においては以下の様な
欠点を生じた。Detailed Description of the Invention (Technical Field) The present invention relates to a method for manufacturing a semiconductor device, and in particular, a method for manufacturing a semiconductor device including a step of implanting ions from above a polysilicon layer to form a diffusion layer and a polysilicon extraction electrode. 0 (Prior art) There is a document "PSA-A NE" for a method of manufacturing a bipolar polycrystalline silicon integrated circuit in which a diffusion layer and a polysilicon extraction electrode are formed by ion implantation from above a polysilicon layer.
W Approach for Bipolar LSI
”in IEEE Vol 5C-13, No 5
PSA (Po
ly-silicon 5elf Align) process, and using this as an example, the prior art will be explained with reference to Fig. An oxide film 13a is formed using a so-called retrograde saponification method, and a P-type impurity layer 14 (base portion) is formed using an ion implantation method. Thereafter, an oxide film 13b is formed using the selective thinning method after the M layer of polysilicon by low pressure vapor phase growth. Next, using a photoresist mask through the polysilicon layer 17, N-type? 4.) Once the impurity is applied, for example, As (arsenic) is implanted into the ivy portion and the collector contact portion by an ion implantation method, and then heat treatment is performed to obtain the emitter portion 15 and the collector contact portion 16 as an N-type impurity layer. For example, a metal wiring electrode made of aluminum gas batter is formed into a wave layer by an evaporation method, and then patterned by photoresist and etching techniques to form a metal wiring layer 113 to obtain the structure shown in FIG. 111 according to the conventional manufacturing method. The polysilicon layer containing N-type impurities on the upper edge of the emitter, rib 15 and collector contact portion 16 serves as an extraction electrode that connects the diffusion layer and the metal wiring electrode, and is infiltrated with gold such as aluminum. It should be noted that it is necessary to have a shallow emitter (having a strong Bayer property that does not destroy the joint). (Disadvantages of the conventional manufacturing method) However, the structure of the conventional manufacturing method described above has the following points. This resulted in some shortcomings.
（１）ポリシリコンを介してイオン注入を行ない、しか
るｔｉ ？ｉ＞処理を行なってエミ、；り部１５で示さ
れるＮ型尚沢度不純物層を形成する場合通ｎイオ／注入
後の最大濃度が１０ ” 〜１０２２ ａ ｔｏｍ ／
ｃｍ３にも達する注入量を必要とするが、これを引き
継き行なう熱部４理によシ安定して熱拡散するのは容易
でない、即ち特に浅い接合に於は熱如理輻鹿・時間依存
性が極端に筒くコントロール性が悪い。(1) Ion implantation is performed through polysilicon, and then ti? When forming an N-type smooth impurity layer as shown in the groove 15 by performing the emitter treatment, the maximum concentration after implantation is 10'' to 1022 atom/n ions/.
A injection amount of up to cm3 is required, but it is not easy to stably diffuse the heat through the heat section that takes over this process. It is extremely dependent and has poor controllability.
さらにはポリシリコン中の局部拡散によってエミッター
ペース接合が不安定、ペース機会が破興され易い。Furthermore, the emitter paste junction becomes unstable due to local diffusion in the polysilicon, and the paste opportunity is easily destroyed.
（２）第１図の１７で示されるエミッタ部１５上方の高
濃関不純物を含むポリシリコン層は該エミッタ部と後に
形成されるへ己線金属１８（例えばアルミニウム）間の
バイヤ一層としての役卵」を必要とするが、烏濃度不純
物を含むゆえに配線層？Ａ例えはアルミニウム（ＡＪ）
との反応が冗長され下方のエミ、り接合が破壊され易い
。等の欠点があり、この為半導体装置の歩留を低下させ
、かつ信頼性の低いものくしていた。(2) The polysilicon layer containing highly concentrated impurities above the emitter section 15 indicated by 17 in FIG. ``Egg'' is required, but since it contains impurities, is it a wiring layer? A example is aluminum (AJ)
The reaction is redundant and the lower emitter junction is likely to be destroyed. These drawbacks have resulted in lower yields and lower reliability of semiconductor devices.
（発明の目的）
本発明の目的は、ポリシリコン層上から不純物をイオン
注入して拡散層とポリシリコンの引き出り、を極とを形
成する工程を含む半導体装置のｔ′！造刀法に於て上記
欠点を解消し高歩留、高品質の製造方法を提供すること
にある。(Object of the Invention) An object of the present invention is to form a semiconductor device t' which includes a step of ion-implanting impurities from above a polysilicon layer to form a diffusion layer, a polysilicon extraction layer, and a pole. It is an object of the present invention to provide a manufacturing method with high yield and high quality by eliminating the above-mentioned drawbacks in the sword manufacturing method.
（発明の構成）
本発明の製造方法はポリシリコン層内部に薄い酸化皮層
を形成し、しかる後イオン注入を該ポリシリコン層内部
の薄い酸化皮層上方にのみ限定して打込み（注入エネル
ギー、注入量でコントロール出来る）（７かる後熱処理
を行なうことを４″ｆ＠とする。(Structure of the Invention) In the manufacturing method of the present invention, a thin oxide layer is formed inside a polysilicon layer, and then ions are implanted only above the thin oxide layer inside the polysilicon layer (implantation energy, implantation amount). (can be controlled by 4" f@) (7) Post-heat treatment is performed.
（実施例） 本発明の実施例について第２図を参照して説明する。(Example) An embodiment of the present invention will be described with reference to FIG.
まず第２図に示す様にｐｇシリコン基板２１上にＮ型エ
ピタキシャル層２２を形成し選択酸化法を用いて酸化膜
２３ａを形成し、イオン注入法等でＰ型不純物層２４゛
（ペース部）を形成する。上記迄は従来４法と同一であ
る。しかる後ポリシリコンを減圧気相成長法等で形成す
るが本発明の製法を達成する為、該ポリシリコン成長時
に成長途中で、例えば歳゛（、す間酸素等の酸化性ガス
を導入すさらにポリシリコンの成長を続けることで第２
図の２７ａ、２９．２７ｂで示す様なポリシリコン層内
に酸化皮層を有する構造を得る。しかる後Ｎ型窩り度不
純物例えばヒ素をエミッタ部２５．コレクタコンタクト
部２６へイオン注入するが住人エネルギー、注入量をフ
ントロールすることによりポリシリコン層内に形成され
た酸化皮層上部のみ限定（第２図の２７ｂで示す上部ポ
リシリコン層内）して不純物を打込み、しかる後熱処理
により拡散してエミッタ部２５とコレクタコンタクト部
２６を得る。次いて従来法と同様金輪配線電極としての
例えばアルミニウムがスバ、ター又ハ蒸着法によシ被着
されて、後ホトレジスト、エッーテング技術によりパタ
ーン形成金属配線ｌｅｔ ２８となり第２図で示す本特
許の製法による構造を得る。First, as shown in FIG. 2, an N-type epitaxial layer 22 is formed on a pg silicon substrate 21, an oxide film 23a is formed using a selective oxidation method, and a P-type impurity layer 24' (paste part) is formed using an ion implantation method. form. The steps up to the above are the same as the four conventional methods. Thereafter, polysilicon is formed by a low pressure vapor phase growth method, etc., but in order to achieve the manufacturing method of the present invention, during the growth of the polysilicon, for example, an oxidizing gas such as oxygen is introduced during the growth. Continuing the growth of polysilicon will lead to a second
A structure having an oxide skin layer within the polysilicon layer as shown at 27a, 29.27b in the figure is obtained. Thereafter, an N-type pitting impurity such as arsenic is added to the emitter section 25. Ions are implanted into the collector contact portion 26, but by controlling the energy and implantation amount, the impurities are limited to the upper part of the oxide layer formed in the polysilicon layer (inside the upper polysilicon layer shown as 27b in FIG. 2). is implanted and then diffused by heat treatment to obtain an emitter portion 25 and a collector contact portion 26. Next, as in the conventional method, for example, aluminum is deposited as a metal ring electrode by a sputtering, tar or ferrite vapor deposition method, and then a pattern is formed by photoresist and etching techniques to form a metal wiring let 28 as shown in FIG. Obtain structure by manufacturing method.
（発明の作用と効果）
本発明の夷造刀法により以下に示す様な顕著な効果を有
する。(Operations and Effects of the Invention) The sword making method of the present invention has the following remarkable effects.
（１）ポリシリコン層内部に数Ａ−Ｑ十Ａの酸化ＰＦ、
層を鳴し、さらに該酸化皮層上刃のポリシリコン層２７
ｂＫＩ−１ｉ定して＾臘厩不純物をイオン注入すること
により欠いて行なわれる熱処理の温度、時間ｇ＝性が安
定化しコントロール性が改善された、こｒＬ ｔｉｔ
ｋ ２図の２７ｂで示される上部ポリシリコン層円に限
定してイオン注入された高濃度不純物が仄いて行なわれ
る熱処理に於て前記酸化皮層２９によって、その拡散を
コントロールされる為１ある。即ちポリシリコン中の不
純物局部拡散が無くなってエミ、り・ベース接合が安定
化、ベース接合の破壊が無くなった。(1) Oxidized PF of several A-Q10A inside the polysilicon layer,
layer, and further the polysilicon layer 27 of the blade on the oxide skin layer.
By ion-implanting impurities at a constant temperature, the temperature and time g of the heat treatment that is required are stabilized and the controllability is improved.
This is because the diffusion of high-concentration impurities ion-implanted into the upper polysilicon layer circle indicated by 27b in FIG. 2 is controlled by the oxide layer 29 during heat treatment. In other words, the local diffusion of impurities in polysilicon is eliminated, the emitter/reverse/base junction is stabilized, and the base junction is no longer destroyed.
（２）内部に酸化度ＮｌＩ２９を有し高濃度不純物を含
むポリシリコン層１％にエミッタ部２５と後に形成され
る配線金属（例えはアルミニウム）間のバイヤー性を向
上させ、該金属が浸透して下方のエミッタ接合を破壊す
るという問題を解決できた０ポリシリコン層内の該酸化
皮層は高濃度不純物をもむ為に充分な導通性を有する、
即ち引き出し負極としての役割は充分はた′すことを付
記しておく。(2) In the 1% polysilicon layer which has an oxidation degree of 29 NlI inside and contains high concentration impurities, the buyer property between the emitter part 25 and the wiring metal (for example, aluminum) to be formed later is improved, and the metal penetrates. The oxide skin layer within the polysilicon layer has sufficient conductivity to absorb high concentration impurities, which solves the problem of destroying the emitter junction below.
In other words, it should be noted that it fully fulfills its role as a negative electrode.
以上のごとく本発明の製法によって従来製法での欠点を
全て解消出来て高歩留、面品質の製造方法を提供できた
。As described above, the manufacturing method of the present invention can eliminate all the drawbacks of conventional manufacturing methods and provide a manufacturing method with high yield and surface quality.
なお、本発明に於ては、ポリシリコン層内の薄い酸化皮
膜を１層に限定することなく多層であっても有効である
ことは勿論である。但し多層の場合、イオン圧入時の不
純物は少なくとも最下層の酸化皮膜より上部に限定して
打込むことを前提とする。Note that, in the present invention, the thin oxide film in the polysilicon layer is not limited to one layer, but it is of course effective even if it is multilayered. However, in the case of a multilayer structure, it is assumed that impurities during ion implantation are limited to at least an area above the oxide film of the lowest layer.
第１図は、従来製法を説明する為の要部断面図、第２図
は、本発明の製法を一実施例によシ説明する為の要部断
面図である。
１１．２１・・・・・・Ｐｆｆｌシリコン、１２．２２
・・・・・・コレクタ部、１３ ａ、 １３ｂ、 ２３
ａ、 ２３ ｂ−・・・・・シリコン酸化１に、１４
．２４・・・・・・ヘース部、１５．２５・・・・・・
エミッタ部、１６．２６・・・・・・コレクタコンタク
ト部、 １７ 、２７ ａ 、 ２７ ｂ−・−ポリ
シリコン層、１８．２８・・・・・・全便配線、２９・
・・・・・ｉ−、ぜ化皮層。FIG. 1 is a sectional view of a main part for explaining a conventional manufacturing method, and FIG. 2 is a sectional view of a main part for explaining a manufacturing method of the present invention according to an embodiment. 11.21...Pffl silicon, 12.22
...... Collector section, 13 a, 13 b, 23
a, 23 b-...silicon oxide 1, 14
．． 24...Heath section, 15.25...
Emitter section, 16.26...Collector contact section, 17, 27a, 27b--Polysilicon layer, 18.28...All wiring, 29.
...i-, keratinized cortex.
Claims (1)
引き出し電極とを形成する工程を含む半導体装置の製造
方法に於て、前記ポリシリコン層内には薄い酸化皮膜を
形成し次いて行なわれるイオン圧入時の不純物を該ポリ
シリコン層内酸化皮膜上部にとどめてしかる後熱処理を
行ない拡散層と引き出し電極とを形成することを特徴と
する半導体装置の製造方法。In a method for manufacturing a semiconductor device that includes a step of ion-implanting impurities from above a polysilicon layer to form a diffusion layer and an extraction electrode, a thin oxide film is formed in the polysilicon layer, and then ion implantation is performed. 1. A method of manufacturing a semiconductor device, comprising the steps of retaining impurities during press-fitting above the oxide film in the polysilicon layer and then performing heat treatment to form a diffusion layer and an extraction electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59213855A JPS6191961A (en) | 1984-10-12 | 1984-10-12 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59213855A JPS6191961A (en) | 1984-10-12 | 1984-10-12 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6191961A true JPS6191961A (en) | 1986-05-10 |
| JPH0418693B2 JPH0418693B2 (en) | 1992-03-27 |
Family
ID=16646136
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59213855A Granted JPS6191961A (en) | 1984-10-12 | 1984-10-12 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6191961A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6486558A (en) * | 1987-09-29 | 1989-03-31 | Toshiba Corp | Manufacture of semiconductor device |
| JPH03147333A (en) * | 1989-11-02 | 1991-06-24 | Nec Corp | Semiconductor device |
| JPH04329641A (en) * | 1991-04-30 | 1992-11-18 | Nec Ic Microcomput Syst Ltd | Npn bipolar transistor |
-
1984
- 1984-10-12 JP JP59213855A patent/JPS6191961A/en active Granted
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6486558A (en) * | 1987-09-29 | 1989-03-31 | Toshiba Corp | Manufacture of semiconductor device |
| JPH03147333A (en) * | 1989-11-02 | 1991-06-24 | Nec Corp | Semiconductor device |
| JPH04329641A (en) * | 1991-04-30 | 1992-11-18 | Nec Ic Microcomput Syst Ltd | Npn bipolar transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0418693B2 (en) | 1992-03-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |