JP2004103715A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem of tradeoff that although reduction in thickness of a collector region is effective for realizing a low V<SB>CE(sat)</SB>, breakdown voltage deteriorates as the collector region approaches the interface to the base region. <P>SOLUTION: A conduction passage of N type polysilicon is provided to reach a substrate while penetrating the base region and the collector region. Since a current flows through the low resistance conduction passage and does not flow through the high resistance collector region when a transistor is turned on, collector resistance can be decreased and a low V<SB>CE(sat)</SB>can be realized while ensuring the breakdown voltage. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device that reduces a collector-emitter saturation voltage.
[0002]
[Prior art]
At present, low-saturation voltage bipolar transistors (hereinafter referred to as low-saturation transistors) having a reduced collector-emitter terminal voltage (saturation voltage) are often used as transistors for portable devices.
[0003]
An example of a conventional low-saturation transistor will be described with reference to FIGS.
[0004]
FIG. 3 is a cross-sectional structure of the low saturation transistor.
[0005]
An N− type epitaxial layer serving as a collector region 52 is stacked on an N + type silicon semiconductor substrate 51 serving as a low resistivity layer in the collector region. On the surface of the collector region 52, a base region 55 which is a P-type impurity diffusion region is provided. Emitter impurities are implanted and diffused so that the base region 55 has a multi-island shape, and an N ⁺ -type emitter region 57 is formed on the surface of the base region 55.
[0006]
Further, a base electrode 59 and an emitter electrode 60 that are in contact with the base region 55 and the emitter region 57 are provided, and a collector electrode 61 is provided on the back surface of the substrate.
[0007]
FIG. 4 shows an example of a conventional method for manufacturing a low-saturation transistor.
[0008]
FIG. 4A shows a step of forming a collector region. An N− type epitaxial layer is formed on an N + type silicon semiconductor substrate 51 to form a collector region 52. The thickness of the collector region 52 is formed to a predetermined thickness by controlling the gas flow rate and time for epitaxial growth. Thereafter, a first thermal oxide film 53 is formed on the entire surface.
[0009]
Next, a predetermined base region portion of the thermal oxide film 53 is opened by a known photolithography process (FIG. 4B). After a P-type impurity is implanted into the entire surface, impurity ions are diffused by annealing to form a base region 55.
[0010]
Further, a predetermined emitter region portion of the thermal oxide film 33 is opened by a known photolithography process, and N ⁺ type ions are deposited. Thereafter, the N ⁺ type ions are diffused by annealing to form the emitter region 57 (FIG. 4C).
[0011]
Further, a base electrode 59 and an emitter electrode 60 that are in contact with the base region 55 and the emitter region 57 are formed. Further, a collector electrode 61 is formed on the back surface to obtain the final structure shown in FIG.
[0012]
As described above, the conventional low-saturation transistor has a cell structure in which the base region 55 and the emitter region 57 are subdivided, thereby increasing the peripheral length of the emitter and reducing the saturation voltage (see, for example, Non-Patent Document 1). ).
[0013]
[Non-patent document 1]
Osamu Akagi and 3 others, “New Generation Low Saturation Transistor”, Sanyo Electric Technical Report, Sanyo Electric Co., Ltd., June 2002, VOL. 34, no. 1, p. 68-p69
[0014]
[Problems to be solved by the invention]
FIG. 5 shows a concentration profile of a wafer by the above-described manufacturing method. From the surface (Xj = 0), an emitter region 57, a base region 55, and a collector region 52 are formed, and this thickness becomes the thickness of the N− type epitaxial layer. Below the collector region 52 is an N + type semiconductor substrate 51 which is a low resistivity layer. Note that the thicknesses of the emitter region 57, the base region 55, and the collector region 52 are hereinafter referred to as the distance between the interfaces of the respective regions. That is, the thickness of the collector region 52 is the distance between the base region 55 and the N + type semiconductor substrate 51, and the collector region 52 has a low concentration region 52a in which the concentration of the impurity region contained therein is low and uniform. A transition region 52b whose concentration rapidly increases near the interface with the N + type semiconductor substrate 51 is provided.
[0015]
In a low-saturation transistor, it is desirable that the collector-emitter saturation voltage (V _{CE (sat)} ) be low because the power consumption can be reduced. To reduce the collector-emitter saturation voltage (V _{CE (sat)} ), Reduction of resistance is most effective. This is because, as is clear from the concentration profile in the figure, the low concentration region 52a of the collector region has the lowest impurity concentration and the highest resistance in the whole. By reducing this distance, that is, by reducing the thickness of the collector region 52, the collector resistance can be reduced, which can contribute to the reduction of the collector-emitter saturation voltage (V _{CE (sat)} ).
[0016]
However, when the distance of the low concentration region 52a is reduced, the breakdown voltage between the collector and the emitter is reduced. This is because, when the depletion layer that has spread through the low-concentration region 52a due to the application of the reverse bias reaches the N + type semiconductor substrate 51 where the concentration is rapidly increased, the depletion layer cannot further spread and leads to breakdown. That is, since the interface between the collector region 52 and the N + type semiconductor substrate 51 approaches the base region 55, the breakdown voltage is reduced and the breakdown voltage is deteriorated. Therefore, there is a trade-off between the collector-emitter saturation voltage (V _{CE (sat)} ) and the breakdown voltage, and there is a problem that the thickness of the collector region 52 cannot be reduced.
[0017]
The N + type epitaxial layer 51 serving as the collector region 52 is formed by epitaxially growing an N + type semiconductor substrate 51 by mixing impurities into hydrogen, monosilane, silicon tetrachloride, or the like. Since the thickness of the collector region 52 is controlled to a predetermined thickness by controlling the flow rate and time of the gas, variations occur. When the collector region 52 is made thinner in order to reduce the collector resistance, this variation reduces the collector-base voltage (V _CBO ), the collector-emitter voltage (V _CEO ), and the collector-emitter saturation voltage (V _{CE (sat)} There is a problem that has a large effect on the variation in ( ₎ ).
[0018]
[Means for Solving the Problems]
The present invention has been made in view of the various problems described above. First, a semiconductor substrate of one conductivity type, a collector region of one conductivity type provided on the semiconductor substrate, and The provided base region of the opposite conductivity type, one conductivity type semiconductor region provided from the surface of the base region to the semiconductor substrate, and provided on the surface of the base region separated into a plurality by the one conductivity type semiconductor region, respectively. This problem is solved by providing the one-conductivity-type emitter region and a base electrode, an emitter electrode, and a collector electrode contacting the base region, the emitter region, and the collector region, respectively.
[0019]
Further, the impurity concentration of the one conductivity type impurity region is higher than the impurity concentration of the collector region and lower than the impurity concentration of the semiconductor substrate.
[0020]
Second, a semiconductor substrate of one conductivity type, a collector region made of an epitaxial layer of one conductivity type provided on the semiconductor substrate, a base region of the opposite conductivity type provided on the collector region, and a surface of the base region A conductive path provided up to the semiconductor substrate, an emitter region of one conductivity type provided on the surface of the base region separated into a plurality by the conductive path, and the emitter region, the base region and the collector region, respectively. The problem is solved by providing an emitter electrode, a base electrode, and a collector electrode to be in contact.
[0021]
Further, the conductive path is formed by burying a one-conductivity-type semiconductor material in a trench provided in the semiconductor substrate.
[0022]
Further, the impurity concentration of the semiconductor material is higher than the impurity concentration of the collector region and lower than the impurity concentration of the semiconductor substrate.
[0023]
Further, the base region and the emitter region are provided in a plurality of islands.
[0024]
Further, the base region and the emitter region are circular.
[0025]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2 by taking an NPN planar transistor as an example.
[0026]
FIG. 1 shows the structure of the semiconductor device of the present invention. FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along line AA of FIG. 1A.
[0027]
The NPN planar transistor includes a semiconductor substrate 1, a collector region 2, a base region 5, a conductive path 4, an emitter region 7, a base electrode 9, an emitter electrode 10, and a collector electrode 11.
[0028]
The semiconductor substrate 1 is an N + type semiconductor substrate serving as a high resistivity layer of the collector region 2, and an N− type epitaxial layer is grown thereon to form the collector region 2. The N-type impurity concentration of the semiconductor substrate 1 is about 10 ¹⁹ to 10 ²⁰ atoms / cm ³ , and the N-type impurity concentration of the collector region 2 is about 10 ¹⁴ to 10 ¹⁵ atoms / cm ³ .
[0029]
The thickness of the collector region 2 is determined depending on the required breakdown voltage, but in the present embodiment is, for example, about 5 μm to 150 μm. Here, the thickness of the collector region 2 is a distance from the interface with the base region 5.
[0030]
Base region 5 is a P-type impurity diffusion region provided on the surface of collector region 2. The depth from the substrate surface is set to about 2 μm to 30 μm, and the conductive path 4 forms a circular multi-island having a diameter (width) of about 10 μm to 100 μm.
[0031]
The emitter region 7 is an N + -type impurity diffusion region provided on the surface of the base region 5 separated by a plurality of conductive paths 4, and is provided in a circular shape at the center of the multi-island base region 5. The emitter region is formed at a depth corresponding to hFE.
[0032]
The conductive path 4 is a semiconductor region provided from the surface of the base region 5 to the semiconductor substrate 1. As shown in FIG. 1A, a trench 4a is provided at a depth reaching the semiconductor substrate 1 from the surface of the base region 5 in a pattern such that the base region 5 has a circular island shape, and the trench 4a contains an N-type impurity. The polysilicon 4b is buried. The impurity concentration of N-type polysilicon 4b is higher than the impurity concentration of collector region 2 and lower than that of semiconductor substrate 1. ^{Specifically,} it is ^{10 15 ~10 1 9 atoms / cm} 3 or so. As will be described later in detail, the depth of the trench 4a needs to be a depth penetrating the collector region 2. Since the thickness of collector region 2 is determined by the required breakdown voltage, the depth of trench 4a is also set to a predetermined depth according to the required breakdown voltage. In the present embodiment, the depth is set to reach the collector region 2 by about 10 μm to 20 μm.
[0033]
Due to the conductive path 4, the collector region 2 and the base region 5 have a multi-island structure separated into a plurality.
[0034]
Further, a base electrode 9 and an emitter electrode 10 are provided in contact with the base region 5 and the emitter region 7, respectively, and a collector electrode 11 is provided on the back surface.
[0035]
A feature of the present invention resides in providing a conductive path 4 made of N-type polysilicon that penetrates from the surface of the substrate 1 through the collector region 2 and reaches the semiconductor substrate 1.
[0036]
The collector-emitter saturation voltage (V _{CE (sat)} ) of a transistor depends on the driving conditions (collector current and base current) of the transistor, current gain, emitter resistance, and collector resistance. In particular, since the values of the emitter resistance and the collector resistance are directly related to the collector-emitter saturation voltage (V _{CE (sat)} ), reduction of these values reduces the collector-emitter saturation voltage (V _{CE (sat)} ). Is effective.
[0037]
First, the emitter resistance can be reduced by increasing the effective operating area of the emitter region. However, the emitter effective operating area is not simply proportional to the emitter area. Since a voltage drop occurs in the base due to the spreading resistance of the base, the emitter current tends to flow to the periphery of the emitter near the base contact. Therefore, the effective operating area can be increased by increasing the peripheral length of the emitter.
[0038]
That is, as shown in FIG. 1 (or FIG. 5), the base structure and the emitter region are subdivided into a cell structure to increase the emitter peripheral length and reduce the emitter resistance.
[0039]
The N− type collector region 2 is a high resistance layer, and the reduction of the collector resistance is most effective for reducing the collector-emitter saturation voltage (V _{CE (sat)} ). That is, it is possible to reduce the collector resistance by reducing the thickness of the collector region 2 and to reduce the collector-emitter saturation voltage (V _{CE (sat)} ).
[0040]
However, when the thickness of the collector region 2 is reduced, the distance between the low-concentration regions 52a shown in FIG. 5 is reduced, and the breakdown voltage between the collector and the emitter is reduced. This is because, as described above, when the depletion layer that has spread in the low-concentration region due to the application of the reverse bias reaches the N + type semiconductor substrate in which the concentration rapidly increases, the depletion layer cannot further spread and leads to breakdown. .
[0041]
That is, when the interface between the collector region 2 and the N + type semiconductor substrate 1 is brought closer to the base region 5, the breakdown voltage is reduced and the breakdown voltage is deteriorated. As described above, the collector-emitter saturation voltage (V _{CE (sat)} ) and the breakdown voltage have a trade-off relationship, and there is a problem that the thickness of the collector region 2 cannot be simply reduced.
[0042]
Therefore, in the structure of the present invention, a conductive path 4 made of an N-type semiconductor region penetrating through the collector region 2 and reaching the N + type substrate 1 is provided. By making the impurity concentration of the conductive path 4 higher than that of the collector region 2 and lower than that of the semiconductor substrate 1, when the transistor is turned on, the conductive path 4 is removed from the base region 5 as shown in FIG. As a result, a current flows through the substrate 1. That is, current does not pass through the collector region 2 of the conventional high-resistance layer but flows through the low-resistance region, so that the collector-emitter saturation voltage (V _{CE (sat)} ) can be reduced.
[0043]
On the other hand, since the thickness of the collector region 2 may be the same as that of the related art, a low V _{CE (sat)} can be realized while maintaining the withstand voltage as before. Furthermore, since the current passes through the conductive path 4, there is no need to consider the resistance of the collector region 2. That is, the collector region 2 can be further thickened and the withstand voltage can be further improved as long as the formation of the trench 4a is possible in the process.
[0044]
Here, a method for manufacturing a semiconductor device of the present invention will be described with reference to FIG.
[0045]
First Step: An N + type semiconductor substrate 1 to be a low resistivity layer of the collector region 2 is prepared. An N− type epitaxial layer is grown on a substrate 1 to form a collector region 2. The collector region 2 is formed to have a thickness of about 5 μm to 150 μm from the surface in consideration of withstand voltage.
[0046]
Next, a P + type impurity is ion-implanted and diffused into the surface of the collector region 2 to form a base region 5 at a depth of 2 μm to 30 μm from the surface (FIG. 2A).
[0047]
Second Step: The trenches 4a are formed at regular intervals so that the base region 5 has a circular shape with a diameter (opening width) of about 10 μm to 100 μm. The trench 4 a is formed to a depth that penetrates the collector region 2 from the surface of the substrate 1 and reaches the substrate 1. In this embodiment, it is assumed that the substrate reaches about 10 μm to 20 μm. The base region 5 and the collector region 2 are separated into a multi-island shape by a trench (FIG. 2B).
[0048]
After that, an N-type polysilicon 4b is deposited on the entire surface and then etched back. Thereby, N-type polysilicon 4b is buried in trench 4a, and conductive path 4 is formed. Further, reflow is performed at 1000 ° C. for about 20 minutes to activate impurities in the conductive path 4. The impurity concentration of the conductive path 4 is higher than the impurity concentration of the collector region 2 and lower than the impurity concentration of the substrate 1. That is, when the transistor is turned on, a current passes through the conductive path 4, so that the collector resistance can be reduced. Further, since the thickness of the collector region 2 may be the same as the conventional one, it is possible to reduce the collector resistance while securing the withstand voltage.
[0049]
Third Step: In order to form the emitter region 7, the oxide film provided after the heat treatment of the base region 5 is removed. The emitter region 7 is formed by diffusing an N ++ type impurity in a circular shape at the center on the surface of the base region 5 separated into a plurality by the conductive path 4. Thereafter, after an insulating film is formed on the entire surface, a contact with the base region 5 and the emitter region 7 is opened, and a base electrode 9 contacting the base region 5 and an emitter electrode 10 contacting the emitter region 7 are formed. The collector electrode 11 is formed to obtain a final structure.
[0050]
【The invention's effect】
As described above, according to the present invention, it is possible to realize a low V _{CE (sat)} while securing a required breakdown voltage.
[0051]
For realizing low V _{CE (sat)} , reduction of the collector resistance, which is a high resistance layer, is most effective. The collector resistance can be reduced by reducing the thickness of the collector region. However, since the collector region is close to the base region, the breakdown voltage is deteriorated, and the two have a trade-off relationship. Therefore, in the present embodiment, a high-concentration conductive path that penetrates the collector region and reaches the substrate is provided, and when the transistor is turned on, the conductive path is passed without passing through the collector region.
[0052]
As a result, the collector resistance can be reduced, so that low V _{CE (sat)} is realized. Further, at this time, since the collector thickness may be the same as the conventional one, the _{VCE (sat)} becomes low while the withstand voltage is maintained.
[0053]
Further, since the current passes through the conductive path, it is not necessary to consider the collector resistance, that is, the thickness of the collector region. That is, as long as trench formation is possible in the process, the thickness of the collector region can be increased, the withstand voltage can be further improved, and low _{VCE (sat)} can be realized.
[Brief description of the drawings]
FIG. 1A is a plan view and FIG. 1B is a cross-sectional view for explaining the present invention.
FIG. 2 is a cross-sectional view for explaining the present invention.
3A is a plan view and FIG. 3B is a cross-sectional view for explaining a conventional technique.
FIG. 4 is a cross-sectional view for explaining a conventional technique.
FIG. 5 is a characteristic diagram for explaining a conventional technique.

Claims (7)

A semiconductor substrate of one conductivity type;
A collector region of one conductivity type provided on the semiconductor substrate,
A reverse conductivity type base region provided on the collector region,
One conductivity type semiconductor region provided from the surface of the base region to the semiconductor substrate,
An emitter region of one conductivity type provided on the surface of the base region separated into a plurality by the semiconductor region of one conductivity type,
A semiconductor device comprising: a base electrode, an emitter electrode, and a collector electrode that are in contact with the base region, the emitter region, and the collector region, respectively. 2. The semiconductor device according to claim 1, wherein the impurity concentration of the one conductivity type impurity region is higher than the impurity concentration of the collector region and lower than the impurity concentration of the semiconductor substrate. A semiconductor substrate of one conductivity type;
A collector region comprising a one conductivity type epitaxial layer provided on the semiconductor substrate,
A reverse conductivity type base region provided on the collector region,
A conductive path provided from the surface of the base region to the semiconductor substrate,
An emitter region of one conductivity type provided on the surface of the base region separated into a plurality by the conductive path,
A semiconductor device comprising: an emitter electrode, a base electrode, and a collector electrode that are in contact with the emitter region, the base region, and the collector region, respectively. 4. The semiconductor device according to claim 3, wherein the conductive path is formed by burying one conductivity type semiconductor material in a trench provided in the semiconductor substrate. 5. The semiconductor device according to claim 4, wherein the impurity concentration of the semiconductor material is higher than the impurity concentration of the collector region and lower than the impurity concentration of the semiconductor substrate. 4. The semiconductor device according to claim 1, wherein the base region and the emitter region are provided in a plurality of islands. 5. 4. The semiconductor device according to claim 1, wherein said base region and said emitter region are circular.

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