JP2001274395A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device for realizing high breakdown voltage and low on-resistance and reducing the number of steps of epitaxial growth, and to provide its manufacturing method. SOLUTION: An n- epitaxial layer 12A is formed on a n+ semiconductor substrate 1a and a (p) buried layer 13A is formed in the epitaxial layer 12A. An n- epitaxial layer 12B with impurity concentration higher than the epitaxial layer 12A and thinner than the epitaxial layer is formed on the epitaxial layer 12A, and a (p) buried layer 13B is formed in the epitaxial layer 12B. An n- epitaxial layer 12C is formed with impurity concentration higher than the epitaxial layer 12A and thinner than the epitaxial layer 12A is formed on the epitaxial layer 12B. A base layer 14 and a source layer 15 are formed at the epitaxial layer 12C, and a drain electrode is formed on the backside of the semiconductor substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a power MOS switching element which requires a low on-resistance and a high breakdown voltage, and a method of manufacturing the same.

[0002]

2. Description of the Related Art A conventional planar type power MOS transistor used for a switching element will be described.

FIG. 8 shows a conventional planar type power MOS.
FIG. 3 is a cross-sectional view illustrating a structure of a transistor.

As shown in FIG. 8, an n ⁺ semiconductor substrate 101
An n ⁻ epitaxial layer 102 is formed on one surface of the substrate, and the n ⁻ epitaxial layer 102 has a base (p
Layer) 103 and a source (n-layer) 104 are formed.
On the base (p layer) 103, a gate 106 is formed via a gate insulating film 105. From the above, MO
An S structure is formed. Also, the n ⁺ semiconductor substrate 101
The drain electrode 107 is formed on the other surface.

In a power MOS transistor having such a structure, a source (n) is supplied from a drain electrode 107 via an n ⁺ semiconductor substrate 101 and an epitaxial layer 102.
A current path to the layer 104 is formed. Therefore, the resistance (ON resistance) when the device is turned on depends on the thickness and the resistivity of the epitaxial layer 102. Further, since the depletion layer extends in the epitaxial layer 102, the breakdown voltage of the power MOS transistor is determined by the thickness and the resistivity of the epitaxial layer 102.

As described above, since the current path and the region for maintaining the breakdown voltage are the same, if the thickness of the epitaxial layer 102 is increased to increase the breakdown voltage, the on-resistance increases, and conversely, the epitaxial layer 102 is reduced in thickness. When the on-resistance is lowered,
There is a contradictory relationship that the breakdown voltage also decreases. Therefore, it is difficult to satisfy both the high breakdown voltage and the low on-resistance. In the above description, n-type and p-type having relatively low concentrations are referred to as “n ⁻ ” and “p ⁻ ”, respectively.
High-concentration n-type and p-type are referred to as “n ⁺ ” and “p ⁺ ”, respectively.

Therefore, devices have been devised that satisfy the requirements of high breakdown voltage and low on-resistance.

FIG. 9 is a cross-sectional view showing the structure of a conventional planar type power MOS transistor which satisfies a high withstand voltage and a low on-resistance.

As shown in FIG. 9, an n ⁺ semiconductor substrate 111
Is formed on one side by repeating formation of an epitaxial layer and formation of a buried layer by ion implantation.
^- epitaxial layer 112, p layer 113 and the n layer 11,
4 are formed. On the other surface of n ⁺ semiconductor substrate 111, drain electrode 117 is formed. Further, a base, a source, and a gate (not shown) are formed as in a normal device of this type. The p
The layer 113 is formed by ion implantation of boron (B), and the n-layer 114 is formed by ion implantation of arsenic (As).

[0010]

As described above, FIG.
In the power MOS transistor shown in (1), since the current path and the region for maintaining the breakdown voltage are the same, increasing the thickness of the epitaxial layer to increase the breakdown voltage increases the on-resistance. There is a contradictory relationship that lowering the resistance lowers the withstand voltage, and it is difficult to satisfy both.

Further, in the power MOS shown in FIG. 9, it is necessary to repeat the formation of the epitaxial layer and the buried layer a plurality of times (six times in FIG. 9), resulting in an increase in cost.

Therefore, the present invention has been made in view of the above-mentioned problems, and can realize high breakdown voltage and low on-resistance.
It is still another object of the present invention to provide a semiconductor device and a method for manufacturing the same, which can prevent the spread of the buried layer and reduce the manufacturing cost by reducing the number of epitaxial growth steps.

[0013]

In order to achieve the above object, a semiconductor device according to the present invention comprises: a first epitaxial layer of a first conductivity type formed on a semiconductor substrate of a first conductivity type; A plurality of first buried layers of a second conductivity type having a predetermined width and arranged at predetermined intervals in a first epitaxial layer, and a first conductivity type formed on the first epitaxial layer. A second epitaxial layer, a plurality of second buried layers of a second conductivity type having a predetermined width and arranged at predetermined intervals in the second epitaxial layer, and the second epitaxial layer And a third epitaxial layer of the first conductivity type formed thereon.

Further, in the semiconductor device, the second buried layer has a width and an interval substantially equal to those of the arranged first buried layers, and the first buried layer has a first width in a direction perpendicular to a surface of the semiconductor substrate. It is characterized in that it is arranged at a position substantially coincident with the buried layer.

Further, the semiconductor device may further include a first device.
The conductive type second and third epitaxial layers have a higher impurity concentration than the first epitaxial layer.

Further, the semiconductor device is characterized in that the thickness of the second and third epitaxial layers is smaller than that of the first epitaxial layer.

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a first epitaxial layer of a first conductivity type on a semiconductor substrate of a first conductivity type; Forming an insulating film on the epitaxial layer, etching the insulating film in a stripe shape, and striping the first epitaxial layer on which the striped insulating film is formed by ion implantation. Forming a first buried layer of the second conductivity type, and having a higher impurity concentration and a smaller thickness of the first conductivity type on the first epitaxial layer as compared with the first epitaxial layer. Forming a second epitaxial layer; forming an insulating film on the second epitaxial layer; etching the insulating film in a stripe shape; Forming, by ion implantation, a second buried layer of a stripe-shaped second conductivity type in the second epitaxial layer on which the insulated insulating film has been formed; Forming a third epitaxial layer having a higher impurity concentration of the first conductivity type and a smaller thickness than the first epitaxial layer.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing the structure of a semiconductor device according to a first embodiment of the present invention.

The feature of this semiconductor device is that a p buried layer is formed inside an n epitaxial layer. Further, since the current path is formed between the p buried layer and the p buried layer, the on-resistance depends on the thickness of the epitaxial layer, the concentration, the distance between the arranged p buried layers and the p.
It depends on the width of the buried layer. Since the depletion layer extends not only from the channel portion but also from each of the p buried layers inside the epitaxial layer, the breakdown voltage is the sum of the depletion layers of all the epitaxial layers, and the thickness, concentration, and depth of the p buried layer of the epitaxial layer. Depends on the width in the vertical direction.

This semiconductor device is a planar type power MOS, but has a structure in which an n-type epitaxial layer has a buried layer of an inverse type (p). In order to complete a device with this structure, there are the following problems.

Characteristic degradation (degradation of breakdown voltage, increase of on-resistance, etc.) due to the spread of the p buried layer, characteristic degradation due to the non-optimal thickness and resistance of the epitaxial layer, increase in manufacturing cost due to increase in the number of epitaxial growth processes, thickness of the epitaxial layer And lower yield due to variations in resistivity.

Therefore, for each of the above-mentioned problems,
Optimized structure and manufacturing conditions

First, in order to reduce the characteristics due to the spread of the p-type buried layer, the temperature of the epitaxial growth must be lowered (SiH
Diffusion of the buried layer can be prevented and the characteristics can be improved by optimizing the process heat process by shortening the epitaxial growth (growing with four gases), shortening the epitaxial growth (adopting a single wafer apparatus, increasing the growth rate), and optimizing the process heat process.

In order to prevent the characteristic deterioration due to the non-optimal thickness and resistance of the epitaxial layer and the cost increase due to the increase in the number of epitaxial growth steps, the characteristics are maintained by optimizing the thickness and resistivity of each epitaxial layer. Meanwhile, the number of epitaxial growth steps is reduced.

Further, with respect to a decrease in yield due to a variation in the thickness of the epitaxial layer, the variation in the thickness is reduced by employing a single-wafer type epitaxial apparatus.

The structure and manufacturing method of a semiconductor device which solves the above problems and achieves both high breakdown voltage and low on-resistance will be described below in detail.

As shown in FIG.⁺Of the semiconductor substrate 11
On one side, n⁻The epitaxial layer 12A is formed.
Have been. This n⁻On the epitaxial layer 12A, n
⁻An epitaxial layer 12B is formed, and n⁻Epi
N is placed on the axial layer 12B. ⁻Epitaxial layer 12C
Are formed. Thus, n⁺On semiconductor substrate 11
Has three layers of n⁻Epitaxial layers 12A, 12B, 1
2C are sequentially formed. First layer n⁻Epitaxy
The layer 12A has a concentration of 1.0 × 10^Fifteen[Cm ^-3]so
The thickness is about 25 μm. N of the second and third layers⁻D
The density of the epitaxial layers 12B and 12C is 2.0 × 10
^Fifteen[Cm^-3] And the film thickness is about 10 μm.

The first n ^- epitaxial layer 12A
Near the upper layer inside, a first p-buried layer 13A is formed. As shown in FIG. 1, a plurality of the first p buried layers 13A are arranged while maintaining a predetermined width and a predetermined interval. A second p-buried layer 13B is formed near the upper layer in the second n ^- epitaxial layer 12B. A plurality of the second p-embedded layers 13B are arranged at a position substantially coincident with the arranged first p-embedded layers 13A vertically above the semiconductor substrate surface. The first p buried layer 13A and the second p buried layer 13
B is formed in a stripe shape when viewed from above with respect to the n ⁺ semiconductor substrate 11.

A base (p layer) 14 is formed in the upper part of the n ^- epitaxial layer 12C. further,
A source (n-layer) 15 is formed on the base (p-layer) 14. On the base (p layer) 14, the gate insulating film 1
6, a gate electrode 17 is formed. Also, n
^{+ A} drain electrode 18 on the other surface of the semiconductor substrate 11
Are formed.

In the semiconductor device, the concentrations of the second and third n ^- epitaxial layers 12B and 12C are higher than those of the first n ^- epitaxial layer 12A. Further, the first n ^- epitaxial layer 12A
, The second and third n ⁻ epitaxial layers 12
B and 12C are made thinner. Thus, the on-resistance can be reduced. At the same time, since the concentration of the first n ^- epitaxial layer 12A is not increased, the withstand voltage does not decrease and a high withstand voltage can be maintained.

As described above, according to the semiconductor device of the first embodiment, high breakdown voltage and low on-resistance can be realized.

Next, a method of manufacturing the semiconductor device shown in FIG. 1 will be described.

FIGS. 2A to 2D are cross-sectional views of respective steps showing a method of manufacturing the semiconductor device according to the first embodiment.

First, as shown in FIG. 2A, an n ⁺ semiconductor substrate 11 is epitaxially grown, and n ^+
- forming an epitaxial layer 12A. As the n ⁺ semiconductor substrate 11, a substrate having a concentration of 1.0 × 10 ¹⁹ cm ⁻³ or more (0.006 Ω · cm or less) is used. The first n ⁻ epitaxial layer 12A has a concentration of 1.0 × 10
^A film thickness of about 25 μm is formed at ¹⁵ [cm ⁻³ ].

Subsequently, an oxide film is formed on n ^- epitaxial layer 12A. Then, width 1.0 by RIE method
(0.6 to 1.4) μm, spacing 6.0 (4.0 to 8.0).
0) The oxide film is etched in a stripe shape of about μm. Further, after forming a buffer oxide film having a thickness of about 100 nm, as shown in FIG. 2B, boron (B) is ion-implanted to form a first p-buried layer 1 having a width of 1.0 μm.
3A are formed so as to be arranged at intervals of 6.0 μm. The ion implantation for forming the first p buried layer 13A is performed at an acceleration voltage of 60 to 140 KeV and a dose of 2.0 ×
It is performed at 10 < ¹³ > to 2.0 * 10 ^{< 14} > [cm ^<-2 >]. Although the width of the first p-buried layer 13A was 1.0 μm, the width of the first p-buried layer 13A was 1.0 μm in consideration of the diffusion of the p-buried layer in the second and third epitaxial growth steps described later.
It may be smaller. In the above step, boron is blocked by an oxide film at the time of ion implantation, but may be performed by a resist film instead of the oxide film.

Further, epitaxial growth is performed on the first n ^- epitaxial layer 12A, as shown in FIG.
As shown in FIG. 5, a second n ^- epitaxial layer 12B is formed. The second n ^- epitaxial layer 12B
Has a concentration of 2.0 × 10 ¹⁵ [cm ⁻³ ] and a film thickness of 10 μm.
Degree is formed.

Subsequently, as described above, an oxide film is formed on the second n ^- epitaxial layer 12B. And R
The oxide film is etched in a stripe shape having a width of about 1.0 μm and an interval of about 6.0 μm by the IE method. Further, after a buffer oxide film having a thickness of about 100 nm is formed, boron (B) is ion-implanted into the second n ^- epitaxial layer 12B so that the second p-buried layer 13B having a width of 1.0 μm is formed at intervals of 6 μm. It is formed so as to be arranged at 0.0 μm. The second
The ion implantation for forming the p buried layer 13B of
This is performed under the same conditions as those for forming the first p-buried layer 13A. Note that the second p buried layer 1
The width of 3B is 1.0 μm, but may be smaller than 1.0 μm in consideration of the diffusion of the p-buried layer in the third epitaxial growth step described later.

Further, as shown in FIG. 2C, a third n ^- epitaxial layer 12C is formed on the second n ^- epitaxial layer 12B by epitaxial growth. Like the formation of the second n ^- epitaxial layer 12B, the third n ^- epitaxial layer 12C has a concentration of 2.0 × 10 ¹⁵ [cm ⁻³ ] and a thickness of 10 μm.
Degree is formed.

[0040] Thereafter, as shown in FIG. 2 (d), the third layer the n ^- top of the epitaxial layer 12C, to form the source 15 of the base 14, ^{n +} layer of ^{p +} layer. In addition, 3
The gate insulating film 16 is formed on the n ^- epitaxial 12C layer of the layer. Further, a gate 17 is formed on the gate insulating film 16. Thus, a MOS structure is formed. Further, a drain electrode 18 is formed on the other surface of the n ⁺ semiconductor substrate 11.

In the above manufacturing method, three epitaxies
Of epitaxial layer by double growth, ion injection twice
The formation of the buried layer is performed. First to third layers
N ⁻The combined n of the epitaxial layers 12A to 12C⁻
The thickness of the epitaxial layer is about 45 μm.

In the method of manufacturing a semiconductor device described above,
It has the following features. Although the first n ^- epitaxial layer 12A has a large thickness, in the epitaxial layer growth step, the p-buried layer has not been formed yet and does not affect the diffusion of the p-buried layer. It is not necessary to limit the growth conditions of the epitaxial layer 12A. For example, in a batch processing epitaxial growth apparatus, a high temperature of 1100 to 1150 ° C. and a growth gas of SiHCl are used.
3. It is also possible to perform epitaxial growth at a high growth rate (about 3 μm / min) using SiCl 4.

The thickness of the second and third n ^- epitaxial layers 12B and 12C is smaller than the thickness of the first n ^- epitaxial layer 12A. Further, using a single-wafer type epitaxial apparatus, the low-temperature
C., a high growth rate (about 1-2 μm /
min) to perform epitaxial growth. Accordingly, since the temperature for raising and lowering the temperature is high and the time for the epitaxial growth step is short, it is possible to prevent auto-doping and thermal diffusion of the buried layer. In addition, by using a single-wafer type epitaxial apparatus, variations in the thickness of the epitaxial layer in the wafer surface can be suppressed, and variations in the characteristics in the wafer surface can be reduced.

The results of evaluation of the semiconductor device manufactured by the above-described manufacturing method are as follows. The spread of the p-buried layer (the junction position between the n ^- epitaxial layer and the p-buried layer) could be controlled in the range of 2.8 μm to 3.2 μm. Further, as shown in FIG. 3, the breakdown voltage equivalent to that of the conventional planar type MOS transistor shown in FIG. 8 can be maintained, and the on-resistance can be reduced to about 60% of the conventional level.

[Second Embodiment] A second embodiment of the present invention is the same as the first embodiment, except that the second layer
The third n ^- epitaxial layer has a different concentration configuration, and the other configurations are the same. Therefore, only different portions will be described, and the other components are denoted by the same reference numerals and description thereof will be omitted.

FIG. 4 is a sectional view showing the structure of a semiconductor device according to a second embodiment of the present invention.

The first layer n⁻In the epitaxial layer 12A,
Boron (B) is ion-implanted to form a first p-buried layer 13.
After the formation of A, epitaxial growth is performed, and the first layer
n⁻On the epitaxial layer 12A, as shown in FIG.
High concentration of n⁻Epitaxial layer 12B-1, low concentration of n
⁻Epitaxial layers 12B-2 are sequentially formed. Said high
Concentration of the epitaxial layer 12B-1⁻D
Formed from the surface of the epitaxial layer 12A to a thickness of about 2 μm
And its concentration is 2.0 × 10¹⁶[Cm^-3]
You. The low-concentration epitaxial layer 12B-2 is
8μ thickness from high concentration epitaxial layer 12B-1 surface
m and its concentration is 2.0 × 10 ^Fifteen[C
m^-3].

Subsequently, the epitaxial layer 12B-2
Then, boron (B) is ion-implanted to form a second p-buried layer 13B. The first p buried layer 13A and the second p buried layer 13B are formed in a stripe shape when viewed from above with respect to the n ⁺ semiconductor substrate 11.

Thereafter, epitaxial growth is performed on the epitaxial layer 12B-2, and a high-concentration epitaxial layer 12C-1 and a low-concentration epitaxial layer 12C-2 are sequentially formed as shown in FIG. The high-concentration epitaxial layer 12C-1 is formed as an epitaxial layer 12B-2.
It is formed from the surface to a thickness of about 2 μm, and its concentration is 2.
It is about 0 × 10 ¹⁶ [cm ⁻³ ]. The low-concentration epitaxial layer 12C-2 is formed to a thickness of about 8 μm from the surface of the high-concentration epitaxial layer 12C-1 and has a concentration of 2.0 × 10 ¹⁵ [cm ⁻³ ].
In FIG. 4, the source 15 of the base 14, ^{n +} layer of ^{p +} layer, the gate insulating film 16 are not shown gate 17, and drain electrode 18.

In the semiconductor device configured as described above, compared to the first n ^- epitaxial layer 12A, the semiconductor device
N ^- epitaxial layers 12B-1 and 12B-2 of the third layer and n ^- epitaxial layers 12C-1 and 12C-2 of the third layer
And the thickness of these epitaxial layers is reduced. Thus, the on-resistance can be reduced.

The first n ^- epitaxial layer 12
Since the concentration of A is not high, the breakdown voltage does not decrease. Also, the second n ⁻ epitaxial layers 12B-1 and 3
By increasing the concentration of the n ^- epitaxial layer 12C-1 in the layer, the spread of the p-buried layer can be reduced.

As described above, according to the semiconductor device of the second embodiment, a higher breakdown voltage and a lower on-resistance can be realized, and the buried layer can be further expanded than in the first embodiment. Can be prevented.

In order to evaluate the semiconductor devices of the first and second embodiments, a device for comparison was prepared. This device will be described below as Comparative Examples 1 and 2.

First, the semiconductor device of Comparative Example 1 will be described.

FIGS. 5A to 5D are cross-sectional views of respective steps showing a method for manufacturing a semiconductor device of Comparative Example 1.

As shown in FIG. 5A, an n ⁺ semiconductor substrate 21 is epitaxially grown to form a first n ⁻ epitaxial layer 22A. The n ⁺ semiconductor substrate 2
1 has a concentration of 1.0 × 10 ¹⁹ cm ⁻³ or more (0.00
(6 Ω · cm or less) substrate is used. The first n ⁻ epitaxial layer 22A has a concentration of 1.0 × 10 ¹⁵ [cm ^−
3 ] and a film thickness of about 8.3 μm is formed. Subsequently, FIG.
As shown in (b), boron (B) is ion-implanted on the n ⁻ epitaxial layer 22A to form a first p-embedded layer 23A, and arsenic (As) is ion-implanted to form a first n-embedded layer. The layer 24A is formed.

The process from the formation of the n ⁻ epitaxial layer 22A to the formation of the n buried layer 24A is repeated six times as shown in FIG. Then, as shown in FIG. 5 (d), a thickness of 50μm of the n ^- a stripe (stripe) layer 23 ^- pillar (pillar) layer 24, p. Thereafter, the source of the n ⁺ layer is formed based on the upper part in the p buried layer. Thereby, a MOS structure is formed.

In the semiconductor device of Comparative Example 1 thus configured, the n ^- pillar layer and the p ^- stripe layer are formed, and the manufacturing process until the surface is flattened is the epitaxial growth process six times and the ion implantation. Both boron and arsenic are required 6 times each. Therefore, in this manufacturing process,
Practical application is difficult due to increased manufacturing time and cost.

Next, a semiconductor device of Comparative Example 2 will be described.

FIGS. 6A to 6D are cross-sectional views of respective steps showing a method for manufacturing a semiconductor device of Comparative Example 2.

First, as shown in FIG.⁺Semiconduct
Epitaxial growth is performed on one surface of the body substrate 31.
No, the first layer n⁻An epitaxial layer 32A is formed.
The n ⁺The semiconductor substrate 121 has the same structure as that of Comparative Example 1
And a concentration of 1.0 × 10¹⁹cm^{− 3}(0.006Ω
cm or less). First layer n⁻Epitaxy
Layer 32A has a concentration of 1.0 × 10^Fifteen[Cm^-3]so
It is formed to a thickness of about 13 μm.

Subsequently, an oxide film is formed on n ⁻ epitaxial layer 32A. Then, width 1.0 by RIE method
(0.6 to 1.4) μm, spacing 6.0 (4.0 to 8.0).
0) The oxide film is etched in a stripe shape of about μm. Further, after a buffer oxide film having a thickness of about 100 nm is formed, as shown in FIG. 6B, boron (B) is ion-implanted to form a first p-buried layer 33A. The ion implantation for forming the first p buried layer 33A is performed at an acceleration voltage of 60 to 140 KeV and a dose of 2.0 × 10 ^{13 to} 2.0 × 10 ¹⁴ [cm ⁻² ].

Further, epitaxial growth is performed on the first n ^- epitaxial layer 32A, as shown in FIG.
As shown in FIG. 5, a second n ^- epitaxial layer 32B is formed. The second n ^- epitaxial layer 32B
Is a film having a concentration of 1.0 × 10 ¹⁵ [cm ⁻³ ] and a film thickness of 1 as in the case of forming the first n ⁻ epitaxial layer 32A.
It is formed with a thickness of about 3 μm.

Subsequently, an oxide film is formed on the second n ^- epitaxial layer 32B as described above. And R
The oxide film is etched in a stripe shape having a width of about 1.0 μm and an interval of about 6.0 μm by the IE method. Further, after a buffer oxide film having a thickness of about 100 nm is formed, boron (B) is ion-implanted into the second n ⁻ epitaxial layer 32B to form a second p-buried layer 33B. The ion implantation for forming the second p buried layer 33B is performed under the same conditions as those for forming the first p buried layer 33A.

Further, as shown in FIG. 6C, epitaxial growth is performed on the second n ^- epitaxial layer 32B to form a third n ^- epitaxial layer 32C. The third n ^- epitaxial layer 32C is composed of the first and second n ^- epitaxial layers 32A, 32A.
As in the formation of B, the concentration is 1.0 × 10 ¹⁵ [c
m ^{- 3]} is formed a film thickness of about 13μm in.

[0066] Thereafter, as shown in FIG. 6 (d), the third layer the n ^- top of the epitaxial layer 32C, to form the source 35 of the base 34, ^{n +} layer of ^{p +} layer. In addition, 3
A gate 37 is formed on the n ^- epitaxial 32C layer of the layer via a gate insulating film 36. From the above, MO
An S structure is formed. Further, a drain electrode 38 is formed on the other surface of the n ⁺ semiconductor substrate 31.

In the above manufacturing method, three epitaxies
Of epitaxial layer by double growth, ion injection twice
The formation of the buried layer is performed. First to third layers
N ⁻The epitaxial layers 32A, 32B, 32C are:
They all have the same concentration and the same thickness. In addition,
High temperature (1100 ° C.)
~ 1150 ° C), growth gas SiHCl3 (or Si
HCl3, SiH2Cl2, SiCl4), growth rate 1
Epitaxial growth was performed at μm / min.

In the semiconductor device of Comparative Example 2 manufactured by the above-described manufacturing method, as a result of evaluating the cross-sectional structure,
It was confirmed that the p buried layer was largely spread.
For this reason, the current path was narrowed, and as shown in FIG. 7, it was found that the on-resistance of Comparative Example 2 was higher than that of the first embodiment.

[0069]

As described above, according to the present invention, a high breakdown voltage and a low on-resistance can be realized, and furthermore, the buried layer can be prevented from spreading and the number of epitaxial growth steps can be reduced to reduce the manufacturing cost. It is possible to provide a semiconductor device and a method for manufacturing the same.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention.

FIGS. 2A to 2D are cross-sectional views of respective steps showing a method for manufacturing the semiconductor device of the first embodiment.

FIG. 3 is a diagram showing a relationship between a breakdown voltage and an on-resistance in the first embodiment and the conventional semiconductor device.

FIG. 4 is a sectional view showing a structure of a semiconductor device according to a second embodiment of the present invention.

FIGS. 5A to 5D are cross-sectional views of respective steps showing a method for manufacturing a semiconductor device of Comparative Example 1. FIGS.

FIGS. 6A to 6D are cross-sectional views of respective steps showing a method for manufacturing a semiconductor device of Comparative Example 2. FIGS.

FIG. 7 is a diagram showing the relationship between the spread of a p-buried layer and the on-resistance in the semiconductor devices of the first embodiment and Comparative Example 2.

FIG. 8 is a sectional view showing the structure of a conventional planar type power MOS transistor.

FIG. 9 is a cross-sectional view showing a structure of a conventional planar type power MOS transistor that satisfies conventional high breakdown voltage and low on-resistance.

[Explanation of symbols]

11 n ⁺ semiconductor substrate 12A first n ^- epitaxial layer 12B second n ^- epitaxial layer 12C third n ^- epitaxial layer 12B-1 high-concentration n ^- epitaxial layer 12B-2 ... Low concentration n ^- epitaxial layer 12C-1 ... High concentration epitaxial layer 12C-2 ... Low concentration epitaxial layer 13A ... First p buried layer 13B ... Second p buried layer 14 ... Base (p layer) 15 ... Source (n layer) 16 ... Gate insulating film 17 ... Gate 18 ... Drain electrode

Claims (9)

[Claims] A first conductive type first epitaxial layer formed on a first conductive type semiconductor substrate; and a first epitaxial layer having a predetermined width and being arranged at predetermined intervals in the first epitaxial layer. A plurality of first buried layers of the second conductivity type; a second epitaxial layer of the first conductivity type formed on the first epitaxial layer; and a predetermined width in the second epitaxial layer. And a plurality of second buried layers of the second conductivity type arranged and arranged at a predetermined interval, and a third epitaxial layer of the first conductivity type formed on the second epitaxial layer. A semiconductor device characterized by the above-mentioned. 2. The second buried layer has a width and an interval substantially equal to those of the arranged first buried layers, and substantially coincides with the first buried layer in a direction perpendicular to a surface of the semiconductor substrate. 2. The semiconductor device according to claim 1, wherein the semiconductor devices are arranged at positions. 3. The first and second epitaxial layers of the first conductivity type have a higher impurity concentration of the first conductivity type than the first epitaxial layer.
A semiconductor device according to claim 1. 4. The second and third epitaxial layers,
4. The semiconductor device according to claim 3, wherein the thickness is smaller than that of the first epitaxial layer. 5. The second epitaxial layer of a first conductivity type, a first layer formed on a surface of the first epitaxial layer, a first layer formed on the first layer, and a first layer formed on the first layer. A second layer having an impurity concentration lower than that of the second epitaxial layer;
A third layer formed on the surface of the epitaxial layer of
5. The semiconductor device according to claim 4, further comprising a fourth layer formed on the third layer and having a lower impurity concentration than the third layer. 6. A base layer of a second conductivity type formed on an upper part of the third epitaxial layer, a source layer of a first conductivity type formed in the base layer, and a gate on the base layer A gate electrode formed with an insulating film interposed therebetween; and a drain electrode formed on the other surface of the semiconductor substrate on which the first epitaxial layer is formed, opposite to the one surface. The semiconductor device according to claim 1, 4 or 5, wherein: 7. A step of forming a first epitaxial layer of the first conductivity type on a semiconductor substrate of the first conductivity type; a step of forming an insulating film on the first epitaxial layer; A step of etching in a stripe shape, a step of forming a first buried layer of a second conductivity type in a stripe shape by an ion implantation method in the first epitaxial layer on which the stripe-shaped insulating film is formed, Forming a second epitaxial layer having a higher impurity concentration of the first conductivity type and a smaller thickness on the first epitaxial layer as compared with the first epitaxial layer; Forming an insulating film thereon; etching the insulating film in a stripe shape; and forming an ion on the second epitaxial layer on which the stripe-shaped insulating film is formed. Forming a stripe-shaped second buried layer of a second conductivity type by an implantation method; and a step of forming the first conductivity type with a higher impurity concentration on the second epitaxial layer than in the first epitaxial layer. Forming a third epitaxial layer having a small thickness. 8. The step of forming a second epitaxial layer includes forming a first layer on a surface of the first epitaxial layer, and having a lower impurity concentration on the first layer than on the first layer. Forming a lower second layer, wherein forming the third epitaxial layer includes forming a third layer on a surface of the second layer, and forming a third layer on the third layer. 8. The method according to claim 7, further comprising the step of forming a fourth layer having a lower impurity concentration than the third layer. 9. The method according to claim 9, wherein a second epitaxial layer is formed in the third epitaxial layer.
Forming a conductive type base layer; forming a first conductive type source layer in the base layer; forming a gate electrode on the base layer via a gate insulating film; The semiconductor device according to claim 7, further comprising: forming a drain electrode on the other surface of the semiconductor substrate on which the first epitaxial layer is formed, opposite to the one surface. Device manufacturing method.