JPH06232147A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To form diffused emitter layer extremely shallow and even without extending the LSI manufacturing term for accelerating the bipolar transistor actuation. CONSTITUTION:An emitter aperture part 11 is opened in an emitter forming region of an insulating film provided on an N-type semiconductor substrate wherein P-type base regions 9, 10 of bipolar transistor are formed. Next, polysilicon films 13, 15 in mutually different arsenic contents are laminated for thermally diffusing the arsenic in the base regions to form an emitter region 17. Besides, the arsenic content of polysilicon film 15 is specified to be less than that of the polysilicon film 13. Furthermore, a silicon oxide film 14 in film thickness not exceeding 5nm is to be interposed between the polysilicon films 13 and 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a method for forming a bipolar transistor and its extremely shallow emitter region.

[0002]

2. Description of the Related Art Bipolar LSIs are mainly used for central operators of supercomputers, etc. due to their high speed, but with the recent advances in performance, higher speeds are required for bipolar LSIs. Has been done.

An example of a method of manufacturing an ultra-high-speed bipolar transistor which can meet such requirements and can form an emitter and a base in a self-aligned manner is 1987.
Year, International Electron
Device Meeting Technical
Digest (Technical digest of International Electron Device Meeting)
P. 375-378.

As a conventional technique, a method of forming the emitter diffusion layer shown in this report will be described with reference to FIG.
As shown in FIG. 5A, a P ⁺⁺ base region 507 is formed in the transistor formation region insulated by the insulating separation layer 504, and a P ⁺ polysilicon film 505 and a silicon oxide film 506 are formed and patterned. N-type semiconductor substrate 5
01 silicon oxide film containing boron (BSG
Film). As shown in FIG. 5B, heat treatment is performed to form a P ⁻ base region 509. Next, FIG.
As shown in (c), by etching the BSG film by the reactive ion etching (RIE) method,
The sidewall insulating film 510 is allowed to remain and an emitter formation region is opened. Then, as shown in FIG. 5D, a polysilicon film 511 containing no impurities is formed by a chemical vapor deposition (CVD) method.
Is deposited over the entire surface, and arsenic is implanted into the polysilicon film 511 by an ion implantation method. Furthermore, the photolithography technique and dry etching are combined to form an N ⁺ polysilicon film 51.
1 is patterned. Continued RTA (Rapid)
Thermal Annealing) to diffuse arsenic from the N ⁺ polysilicon film 511 and boron from the sidewall insulating film 512, and to diffuse the N ⁺ emitter region 513 and P ^+.
The transistor is completed by forming the base region 512.

[0005]

In this conventional manufacturing method, the polycrystalline silicon film 511 is formed as it is without being doped, and then arsenic is ion-implanted to make it a conductor. However, since arsenic is implanted perpendicularly to the substrate in the ion implantation, the polycrystalline silicon film 5 is
11 of the flat portion (P ⁺ polycrystalline silicon film 505,
Arsenic is implanted only into the silicon oxide film 506 or a portion above the P ⁻ base region 509, and it is difficult to implant arsenic into the inclined portion of the surface of the sidewall insulating film 512. Therefore, when impurities are diffused from such a non-uniformly doped arsenic-doped polycrystalline silicon film 511 to form the emitter region 513, the arsenic concentration becomes thinner toward the periphery of the emitter opening and the arsenic concentration becomes uniform. The problem arises that it is difficult to form the emitter region. As described above, when the non-uniform emitter region is formed, a substantial junction area between the base and the emitter becomes small, which makes it difficult to improve the operation speed.

In order to solve such a problem, it is necessary to form an emitter region having a uniform impurity concentration in the horizontal direction in the semiconductor substrate under the emitter opening. For that purpose, the polycrystalline silicon film 511 is uniformly formed. It is necessary to dope with arsenic. Therefore, the application of a technique for growing a polycrystalline silicon film and simultaneously doping arsenic was examined. As an example, a mixed gas of SiH ₄ and AsH ₄ is heated to 550 ° C.
A method of heating to ˜600 ° C. and depositing an arsenic-doped polycrystalline silicon film in a vacuum of about 0.1 Torr was used. When a polycrystalline silicon film 511 having a film thickness of 150 to 200 nm was formed for the transistor of FIG. 5 by such a method, a bipolar transistor having a desired operating speed could be obtained. However, the following new problem arose.

That is, the arsenic-doped polycrystalline silicon film is formed into 10 ²¹ atoms / c necessary for forming the emitter region.
When the film is deposited to have a concentration of at least m ³ , the film forming rate is 0.5 nm / min. Since it was below, 300
~ 400 min. It takes much time and is not practical for mass-producing semiconductor devices. Furthermore, in the step of growing an insulating film on the surface of the arsenic-doped polycrystalline silicon film and providing an opening for emitter electrode connection in this,
When dry etching was performed by the reactive ion etching (RIE) method, various etching gases were examined, but there was a problem that a sufficient etching selection ratio could not be obtained between the arsenic-doped polycrystalline silicon film and the insulating film. It was As a result, the arsenic-doped polycrystalline silicon film is etched when the opening is formed, alloy spikes are generated when the emitter electrode is attached, and the transistor leaks.

Therefore, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of forming an emitter region having a uniform impurity concentration in a horizontal direction in a semiconductor substrate below an emitter opening without prolonging a manufacturing period. To provide.

Still another object of the present invention is to provide a semiconductor device having a small characteristic variation.

[0010]

A first semiconductor device manufacturing method according to the present invention comprises a step of forming a second conductivity type base region in a first conductivity type collector region, and a step of forming the first conductivity type collector region. Forming a first polycrystalline silicon film on one main surface of the base region while adding impurities; forming a silicon oxide film on one main surface of the first polycrystalline silicon film; Forming a second polycrystalline silicon film having no impurities added on one main surface thereof, and then introducing the impurity of the first conductivity type into the second polycrystalline silicon film; and Diffusing the first conductivity type impurity into the base region to form the first conductivity type emitter region.

A second method of manufacturing a semiconductor device according to the present invention comprises a step of forming a second conductive type base region in a first conductive type collector region, and the first conductive type on one main surface of the base region. A first polycrystalline silicon film of the first conductivity type, a step of forming a silicon oxide film on the main surface of the first polycrystalline silicon film, and a step of forming the first conductivity type on the main surface of the silicon oxide film. And forming a second polycrystalline silicon film having an impurity concentration lower than that of the first polycrystalline silicon film, and diffusing the first conductivity type impurity into the base region from the first polycrystalline silicon film. Forming an emitter region of the first conductivity type, forming an insulating film covering the second polycrystalline silicon film, and forming an opening in the insulating film, and then filling the opening in the opening. Connected to crystalline silicon film And a step of forming the emitter electrode.

A semiconductor device according to the present invention comprises a semiconductor substrate having an emitter region, a base region and a collector region formed therein, and an emitter electrode electrically connected to the emitter region, the semiconductor device being connected to the emitter region. And a low-concentration polycrystalline silicon layer connected to the emitter electrode, and a silicon oxide film provided at the interface between the high-concentration and low-concentration polycrystalline silicon layers. It is characterized by that.

The above-mentioned present invention has been achieved by the following circumstances.
That is, the polysilicon film forming the emitter has two roles, one is the role as an arsenic diffusion source for forming the emitter diffusion layer, and the other is the alloy spike prevention film at the time of electrode attachment. As a role. Here, in order to form the emitter region, as described above,
Although an arsenic concentration of 0 ²¹ cm ^-3 or more is required, the polysilicon film for electrode attachment is 5 × 10 ¹⁹ to 5 in terms of electric resistance.
Paying attention to the arsenic concentration of about 10 ²⁰ cm ⁻³ , the inventors have devised to divide each role by separate films. That is, arsenic polysilicon films having different arsenic concentrations are stacked and used. What is important here is to interpose a thin silicon oxide film of 5 nm (nanometer) or less between the two layers of arsenic polysilicon film. Heat treatment is required to form the emitter, but if arsenic interdiffuses during this heat treatment, the concentration on the low-concentration arsenic polysilicon side will increase, which will reduce the selection ratio during RIE. A thin silicon oxide film that is a diffusion barrier for arsenic atoms is essential. The thickness of this silicon oxide film is preferably set to 5 nm or less so as not to increase the electric resistance.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a partial cross-sectional view of an essential part of a bipolar transistor manufactured according to the present invention. In this,
Instead of the conventional polycrystalline silicon film 511 of FIG. 5, N ⁺
-Type polycrystalline silicon film 15, silicon oxide film 14 and N ⁺⁺
A type polycrystalline silicon film 13 is provided. Further, a silicon oxide film 18 is formed thereon, and an aluminum film 20 and a titanium nitride film 19 are formed through openings provided in this film.
The emitter electrode 21 made of N ⁺ type polycrystalline silicon film 1
Connected to 5. P ⁻ and P ⁺ type base regions 10,
An N ⁺ -type emitter region 17 having a uniform junction depth and a wide junction area with the base region is formed in the region 16. The P ⁺ type base region 16 is connected to the P type polycrystalline silicon electrode 6 through the P ^{+ +} type base region 9 around the P ⁺ type base region 16. Further, the N ⁺ type buried layer 2 and the N ⁻ type epitaxial layer 3 serve as an N type collector region.

Next, the manufacturing method of this embodiment will be described with reference to the drawings.

2 to 4 are cross-sectional views in the order of manufacturing steps of one embodiment of the present invention. Not only the main part of the transistor shown in FIG. 1 but also other constituent elements of the transistor such as a collector electrode are shown. The formation method is also shown so as to be clear. First, the N ⁺ type buried layer 2, the N ⁻ type epitaxial layer 3 and the field insulating region 4 are formed on the P ⁻ type semiconductor substrate 1. Next, N-type impurities are selectively introduced into the epitaxial layer 3 to form the collector contact region 5. The N ⁺ type buried layer 2 and the N ⁻ type epitaxial layer 3 serve as an N type collector region. Next, a polycrystalline silicon film is formed on one main surface of the semiconductor substrate 1 by the CVD method. The portion of the polycrystalline silicon film, into which the P-type and N-type impurities are introduced, is later connected to the P-type polycrystalline silicon electrode 6 connected to the P-type base region and the N-type collector region. The N-type polycrystalline silicon electrode 7 serves as each. Next, a silicon oxide film 8 is formed on the surface of this polycrystalline silicon film. Next, the silicon oxide film 8 and the polycrystalline silicon film are patterned. By this patterning,
The polycrystalline silicon film is separated into a P-type polycrystalline silicon electrode 6 and an N-type polycrystalline silicon electrode 7, and an opening for exposing the N ⁻ type epitaxial layer 3 is formed in a portion into which a P type impurity is introduced. It Further, by heat treatment, P-type impurities are diffused from the P-type polycrystalline silicon electrode 6,
^{A ++} type base region 9 is formed. Next, a silicon oxide (BSG) film containing boron is deposited on the entire surface. After that, by heat treatment, boron is diffused from the BSG film into the N ⁻ type epitaxial layer 3 and the P ⁻ type base region 10 is formed.
To form. Next, the BSG film is patterned by the reactive ion etching (RIE) method to form the sidewall insulating film 11 on the side surface of the opening, and the emitter opening 12 surrounded by the sidewall insulating film 11 is formed. In this way, the structure shown in FIG. 2A is obtained.

Next, as shown in FIG. 2B, an N ⁺⁺ type polycrystalline silicon film 13 is formed on the entire surface by a CVD method while adding an N type impurity such as arsenic to a minimum required film thickness. To do. Here, the mixed gas of SiH ₄ and AsH ₃ is 550
C. to 600.degree. C. and deposit in a vacuum of about 0.1 Torr. The minimum required film thickness is, for example, 10 nm. The impurity concentration of the N ⁺⁺ type polycrystalline silicon film 13 is set to, for example, 10 ²¹ atoms / cm ³ or more.

Next, as shown in FIG. 3A, a silicon oxide film 14 having a film thickness of 2 to 3 nm, for example, is formed on the surface of the N-type polycrystalline silicon film 13. This silicon oxide film 14 is, for example, a natural oxide film formed by taking this semiconductor substrate into the atmosphere from a CVD device for the N-type polycrystalline silicon film 13. Alternatively, 0.1 to 1 To
It can also be formed by heating to 600 to 650 ° C. for several minutes in a N ₂ gas atmosphere containing 1% O ₂ in a vacuum of rr. Silicon oxide film 14
The film thickness of is preferably set to 5 nm or less in order not to increase the electric resistance.

Next, as shown in FIG. 3B, the polycrystalline silicon film is grown to 150 to 200 nm without adding impurities.
Is formed by the CVD method. After that, the polycrystalline silicon film is doped with arsenic by an ion implantation method to obtain N ⁺ with an impurity concentration of about 5 × 10 ¹⁹ to 10 ²⁰ atoms / cm ^3.
A type polycrystalline silicon film 15 is formed. Here, the dose amount of this ion implantation is, for example, 5 × 10 ¹⁹ atoms / cm 3.
³ and the implantation energy is, for example, 70 keV. The time required for this ion implantation is about 5 min. Per wafer on which transistors are formed. Is.

Next, as shown in FIG. 4A, N is formed by using a photolithography technique and a dry etching technique.
⁺ Type polycrystalline silicon film 15, silicon oxide film 14 and N
^{The ++} type polycrystalline silicon film 13 is sequentially patterned. After that, Rapid Thermal Annealin
By performing g (RTA), boron and arsenic are diffused from the sidewall insulating film 11 and the N ⁺ type polycrystalline silicon film 13, respectively, and the P ⁺ type base region 16 and the N ⁺ type emitter region 17 are formed. This RTA is performed in a nitrogen atmosphere at a temperature of 1000 ° C. for a heat treatment time of 10 to 20 sec.
And

Next, as shown in FIG. 4B, after the silicon oxide film 18 is formed on the entire surface, the N ⁺ type polycrystalline silicon film 15, the P type polycrystalline silicon electrode 6 and the N ⁺ type polycrystalline film 15 are formed. Contact holes for exposing a part of the silicon electrode 7 are formed in the silicon oxide film 18, respectively. Further, after a titanium nitride film 19 and an aluminum film 20 are sequentially deposited by a sputtering method, patterning is performed by combining a photolithography technique and a dry etching technique to form an emitter electrode 21, a base electrode 22 and a collector made of titanium nitride and aluminum. The electrodes 23 are respectively formed.

Here, how the manufacturing period can be shortened as compared with a conventional manufacturing method capable of forming an emitter region having a uniform impurity concentration in a horizontal direction on a semiconductor substrate below an emitter opening will be described.

As described in the problem to be solved by the invention, it is necessary to form the emitter region of 10 ²¹ atoms / sec.
When a polycrystalline silicon film is deposited while being doped with arsenic so as to have a concentration of ³ cm ³ or more, the film formation rate is 0.5 nm /
min. It was below. Therefore, in order to form the polycrystalline silicon film 13 and the polycrystalline silicon film 15 in the above-described embodiment of the present invention while doping the impurities by the same amount as the total film thickness of 160 to 210 nm, at least 320 to 4
20 min. It takes a lot of time.

On the other hand, in the above-mentioned embodiment, the time required for forming the polycrystalline silicon film 13 while doping the impurities is 20 min. , The time required for forming the silicon oxide film 14 is several minutes. , The time required for forming a non-doped polycrystalline silicon film for the polycrystalline silicon film 15 is 100 to 200 min. , The time required for ion implantation into this film is 5 min. Therefore, the total required time is 130 to 230 min. become. Therefore, the manufacturing period of the polycrystalline silicon film for forming the emitter region can be reduced to about half.

Therefore, according to this embodiment, the N type polycrystalline silicon film formed on the base region is formed into the N ⁺⁺ type and the N type.
^{Since the} thin silicon oxide film 14 is formed on the interface between the ⁺ type polycrystalline silicon films 13 and 15, N type impurities for forming the emitter region 17 are formed from the N ⁺ type polycrystalline silicon film 13. Since it can be sufficiently diffused, the emitter region 17 having a uniform impurity concentration distribution in the horizontal direction with respect to the semiconductor substrate can be formed in the base region below the emitter opening 12. Further, since the N ⁺ -type polycrystalline silicon film 15 has a lower impurity concentration than the N ⁺⁺ -type polycrystalline silicon film 13, even when an opening is provided in the insulating film 18 that covers the N ⁺ -type polycrystalline silicon film 13, it is sufficient for the insulating film 18. Since a high etching selectivity can be obtained, it is possible to prevent the polycrystalline silicon film 15 from being etched and generating alloy spikes when attaching the emitter electrode. Further, since the N ⁺ -type polycrystalline silicon film 15 is formed in a state where no impurities are added, and then the N-type impurities are introduced, the time required for manufacturing is longer than that in the case where the N ⁺ -type polycrystalline silicon film 15 is formed while adding the impurities. Can be shortened. Moreover, since the thin silicon oxide film 14 at the interface prevents mutual diffusion of impurities between the N ⁺⁺ type and N ⁺ type polycrystalline silicon films 13 and 15, N ⁺⁺
Since the N-type and N ⁺ -type polycrystalline silicon films 13 and 15 can exert their respective roles to the maximum extent, the above-described effects can be obtained at the same time, and the characteristic variation is less likely to occur. If the silicon oxide film 14 on the interface is thinly formed, the amount of current necessary for transistor operation can be passed while preventing mutual diffusion of impurities between the N ⁺⁺ type and N ⁺ type polycrystalline silicon films 13 and 15. You can

The invention of the present application is not limited to the above-described embodiment, and various modifications can be made. For example, as shown in FIG. 3A, a semiconductor substrate having a silicon oxide film 13 formed thereon has a film thickness of 190 nm and an arsenic concentration of 5 × 10 ¹⁹ ato.
A low-concentration arsenic polycrystalline silicon film of about ms / cm ³ may be formed while being doped with impurities, and further, patterning for forming an emitter electrode may be performed as in the above-described embodiment. In this way, the N ⁺ -type polycrystalline silicon film 15
Instead of, a low concentration arsenic polycrystalline silicon film can be used to further reduce the electric resistance of the emitter.

[0028]

According to the present invention, the first-conductivity-type polycrystalline silicon film formed on the base region is divided into the first and second polycrystalline silicon films, and the silicon oxide film is formed at the interface thereof. Therefore, the first-conductivity-type impurity for forming the emitter region can be sufficiently diffused from the first polycrystalline silicon film, so that the emitter concentration distribution in the base region below the emitter opening is uniform. Regions can be formed. Furthermore, since the second polycrystalline silicon film is formed in a state where no impurities are added, and then the impurities of the first conductivity type are introduced, the time required for manufacturing is longer than that in the case where the second polycrystalline silicon film is formed while adding impurities. Can be shortened. Moreover, the silicon oxide film on the interface is
Since the mutual diffusion of impurities between the polycrystalline silicon films is prevented, the above-described effects are obtained together, and the first and second polycrystalline silicon films can exert their roles to the maximum, and the characteristic variation is less likely to occur. . If the silicon oxide film at the interface is formed thin, it is possible to pass an amount of current necessary for transistor operation while preventing mutual diffusion of impurities between the first and second polycrystalline silicon films.

According to the present invention, the first conductivity type polycrystalline silicon film formed on the base region is formed into the first and second polycrystalline silicon films.
Since the polycrystalline silicon film is divided and the silicon oxide film is formed on the interface, the first conductivity type impurities for forming the emitter region can be sufficiently diffused from the first polycrystalline silicon film. An emitter region having a uniform impurity concentration distribution can be formed in the base region below the emitter opening. Furthermore, since the second polycrystalline silicon film has a lower impurity concentration than the first polycrystalline silicon film, a sufficient etching selection ratio with respect to the insulating film can be obtained even when the opening is formed in the insulating film covering the second polycrystalline silicon film. The polycrystalline silicon film is etched to prevent the generation of alloy spikes when the emitter electrode is attached. Moreover, since the silicon oxide film on the interface prevents mutual diffusion of impurities between the first and second polycrystalline silicon films, the above-described effects can be obtained together, and the first and second polycrystalline silicon films play their respective roles. Can be exhibited to the maximum, and characteristic fluctuations are less likely to occur. If the silicon oxide film at the interface is formed thin, it is possible to pass an amount of current necessary for transistor operation while preventing mutual diffusion of impurities between the first and second polycrystalline silicon films.

[Brief description of drawings]

FIG. 1 is a partial sectional view of an essential part of a bipolar transistor according to the present invention.

FIG. 2 is a cross-sectional view in the order of manufacturing steps according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view in the order of manufacturing steps according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view in the order of manufacturing steps according to an embodiment of the present invention.

5A to 5C are cross-sectional views in the order of manufacturing steps of a conventional semiconductor device.

[Explanation of symbols]

1 P ⁻ type semiconductor substrate 2 N ⁺ type buried layer 3 N ⁻ type epitaxial layer 4 field insulation region 5 collector contact region 6 P type polycrystalline silicon electrode 7 N type polycrystalline silicon electrode 8 silicon oxide film 9 P ⁺⁺ type base region 10 P ^- -type base region 11 sidewall insulating film 12 emitter opening 13 N ⁺⁺ type polycrystalline silicon film 14 a silicon oxide film 15 N ⁺ -type polycrystalline silicon film 16 P ⁺ -type base region 17 N ⁺ -type emitter region 18 Silicon Oxide Film 19 Titanium Nitride Film 20 Aluminum Film 21 Emitter Electrode 22 Base Electrode 23 Collector Electrode

Claims (6)

[Claims] 1. A step of forming a second conductivity type base region in a first conductivity type collector region, and a step of adding a first conductivity type impurity to a first polycrystalline surface on one main surface of the base region. A step of forming a silicon film, a step of forming a silicon oxide film on one main surface of the first polycrystalline silicon film,
Forming a second polycrystalline silicon film with no impurities added on one main surface of the silicon oxide film, and then introducing the first conductivity type impurity into the second polycrystalline silicon film; A step of diffusing the first conductivity type impurity into the base region from a crystalline silicon film to form the first conductivity type emitter region. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the silicon oxide film prevents impurities from interdiffusing between the first and second polycrystalline silicon films. 3. A step of forming a second conductivity type base region in the first conductivity type collector region, and a step of forming the first conductivity type first polycrystalline silicon film on one main surface of the base region. A step of forming a silicon oxide film on the main surface of the first polycrystalline silicon film, and a step of forming the silicon oxide film on the main surface of the first polycrystalline silicon film, Forming a second polycrystalline silicon film having a low impurity concentration; and diffusing the first conductive type impurities into the base region from the first polycrystalline silicon film to form the first conductive type emitter region. And the second step
A semiconductor device having a step of forming an insulating film covering the polycrystalline silicon film, and a step of forming an opening in the insulating film and then forming an emitter electrode buried in the opening and connected to the second polycrystalline silicon film. Manufacturing method. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the silicon oxide film prevents impurities from interdiffusing between the first and second polycrystalline silicon films. 5. A semiconductor device having a semiconductor substrate having an emitter region, a base region and a collector region formed therein, and an emitter electrode electrically connected to the emitter region, wherein a high-concentration region connected to the emitter region is provided. It further comprises a polycrystalline silicon layer, a low-concentration polycrystalline silicon layer connected to the emitter electrode, and a silicon oxide film provided at an interface between the high-concentration and low-concentration polycrystalline silicon layers. Semiconductor device. 6. The thickness of the silicon oxide oxide film is 5 nm.
The semiconductor device according to claim 5, wherein the semiconductor device is set as follows.