JPH01145808A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To suppress an increase in manufacturing steps, such as ion implantion step and a heat treatment step and to from a deep junction and a supershallow junction simultaneously and stably by one heat treatment by employing a polycrystalline silicon layer having larger particle sizes and a polycrystalline silicon layer having smaller particle sizes. CONSTITUTION:A window is opened at source, drain section 106, and a polycrystalline silicon film 107 having large particle size is formed on one face. Then, a polycrystalline silicon film 108 having large particle size is so etched as to remain, and an oxide film 109 is formed on its surface. Thereafter, a polycrystalline silicon film 112 having small particle size is formed on a whole face, and etched with a mask material 113. After the material 113 is eventually removed, the whole face is ion implanted and heat treated. Then, an impurity diffusing speed in a polycrystalline silicon layer 116 having small particle size is extremely slow and that in the layer 108 is fast. Accordingly, a supershallow junction 114 having 300-500Angstrom of diffusing layer depth and a deep junction 115 having 0.2-0.3mum of depth can be simultaneously formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor integrated circuit device.

[Conventional technology]

Currently, there is active development of microfabrication technology to reduce the planar dimensions of transistors in order to increase their integration and performance, but at the same time, there is also a need to reduce the vertical structure, so shallow junction formation technology is also being emphasized. There is.

For example, in the case of a bipolar transistor, forming a shallow emitter junction reduces the junction capacitance, improving the current gain bandwidth product JT and increasing the speed.

Further, in the case of a MOS transistor, by forming source and drain diffusion layers shallowly, a reduction in junction capacitance and a short channel effect can be alleviated.

For this reason, techniques for forming shallow junctions using polycrystalline silicon films have conventionally been used in ultrahigh-speed devices. For example, there is a method in which the emitter junction of a bipolar transistor is formed by dove diffusion treatment of impurities in a polycrystalline silicon film to form a very shallow junction.

On the other hand, ion implantation was used to form relatively deep junctions such as in the base portion.

[Problem that the invention seeks to solve]

Conventionally, when forming a shallow junction using a polycrystalline silicon film, the depth of the junction was determined by the amount of impurity ions implanted, the heat treatment temperature, and
It was controlled by time. However, if an extremely shallow junction (ultra-shallow junction) is to be formed using this method using conventional techniques, it is necessary to lower the amount of impurity ion implantation and lower the heat treatment temperature. However, in this case, lowering the ion implantation amount will result in an increase in resistance and variations in the diffusion layer, and lowering the heat treatment temperature will result in a decrease in the activation rate of impurity ions and a process limitation in that high-temperature treatment cannot be performed in the subsequent process. A problem arises.

In addition, in order to create an integrated circuit in which bipolar transistors and MOS) transistors coexist on the same substrate, the emitter junction of the bipolar device, which requires an ultra-shallow junction, and the source junction of the MOS) transistor, which is a relatively deep junction, are required. Conventionally, when forming drain regions, as mentioned above, ultra-shallow junctions use impurity diffusion from a doped polycrystalline silicon film, while relatively deep junctions such as source/drain regions are formed using ion implantation. They had to be formed in separate processes.

This means, for example, that the emitter junction depth is at least 100 mm
0 Å or less is required, and the source/drain region is 2
This is because 000 to 3000 people is appropriate. This is because in order to improve characteristics such as reducing the junction capacitance of bipolar transistors and improving the current gain bandwidth product JT, the emitter junction needs to be made ultra-shallow with a thickness of 1000 Å or less, while the source/drain regions need to be made with a thickness of 3000 Å or more. , leading to worsening of the short channel effect. Further, a shallow junction of 1000 Å or less is useful for high integration, but depending on the impurity concentration distribution in the semiconductor substrate, it may lead to an increase in the bottom surface capacitance, which is extremely problematic for increasing the speed of devices. This will be explained using FIG. 5. The impurity concentration distribution of the semiconductor substrate is as shown in 501 in FIG.
If the junction depth is 1000, the Pn junction will exist where the concentration is highest, making it difficult for the depletion layer to expand.

Capacitance is inversely proportional to width (c=-!a!-: C is capacitance, ε is dielectric constant, S is area of depletion layer, d is width of depletion layer)
As the width d of the depletion layer becomes narrower, the capacitance C increases. Therefore, in the case of such an impurity concentration distribution, the source and drain regions are located at a relatively deep junction 2.
It will require 000 to 3000 people.

[Means for solving problems]

The present invention proposes a method for stably forming ultra-shallow junctions and deep junctions simultaneously in a simple manner by using a polycrystalline silicon layer with a large grain size and a polycrystalline silicon layer with a small grain size.

That is, the present invention provides a method for forming ultra-shallow junctions and deep junctions in a semiconductor substrate, which includes a step of forming a first polycrystalline silicon layer, and a step of etching the first polycrystalline silicon layer using a photoresist. , a step of oxidizing the surface of the first polycrystalline silicon layer, and a step of forming a second polycrystalline silicon layer having a grain size different from that of the first polycrystalline silicon layer on the first polycrystalline silicon layer. , a step of etching the second polycrystalline silicon layer so that it does not remain on the first polycrystalline silicon layer, and a step of introducing impurities into the first polycrystalline silicon layer and the second polycrystalline silicon layer. and a step of activating impurities by heat treatment and simultaneously thermally diffusing them to form a diffusion layer in the semiconductor substrate.

One way to control the grain size of the polycrystalline silicon layer is to create at least two thin insulating film layers 301 of 5 to 30 layers during polysilicon growth (see Figure 3(a)). It is possible to prevent this from becoming large. On the other hand, in order to obtain polycrystalline silicon with a large grain size, it is sufficient to form only one thin insulating film layer 301 or not to form it at all (FIG. 3(b)).

When the particle size is controlled in this way, for example 1500~
60 in polycrystalline silicon with a grain size of about 2,500.
The inventors have found that the diffusion speed is approximately four times that in polycrystalline silicon having a particle size of about 0 to 1200 nanometers.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

First, FIGS. 1(a) to 1(a) are vertical cross-sectional views showing the main steps of an embodiment of the present invention. This figure shows an example of a device in which bipolar transistors and MOS transistors are mixed.

FIG. 1(a) shows a selectively thick field oxide film 101 approximately 40mm thick in areas other than those where elements are formed on a silicon substrate 100.
After forming 00 to 10,000 people, M of N channel
OS) A gate oxide film 102 is formed on the part where the transistor is to be formed.
A base region 105 is shown in a portion where a gate electrode 103 and a bipolar transistor are to be formed.

Here, when forming this gate electrode 103, an insulating film 100 grown on top thereof by chemical vapor deposition (CVD) is used.
It has 0 to 3000 people 104.

FIG. 1(b) shows a polycrystalline silicon film 10 with a large grain size formed by opening a window in the source/drain portion 106 by a PR process.
7 is formed on a 2,000 to 5,000-layer surface and further etched until the insulating film 104 above the gate electrode 103 is exposed.

Next, as shown in FIG. 1C, the polycrystalline silicon film 108 with large grain size is etched in the region including the source/drain part 106 in a PR process, and 100 to 500 grains are formed on the surface. An oxide film 109 is formed. A window is then opened in the emitter section 110 to expose the silicon substrate 111.

Next, as shown in FIG. 1(d), a polycrystalline silicon film 1 whose grain size is smaller than that of the polycrystalline silicon film 107 that has already grown.
12 will be formed on the entire surface for 2,000 to 5,000 people.

FIG. 1(e) shows the polycrystalline silicon film 112 having a small grain size left in the emitter forming portion 110 by etching using a suitable mask material 113 such as photoresist. During etching, the oxide film 109 on the polycrystalline silicon film 108 acts as a stopper, ensuring a sufficient selection ratio.

Finally, as shown in FIG.
If N-type impurities, such as arsenic, are introduced into 8 and 116 and heat treated, the impurity diffusion rate in the polycrystalline silicon layer 118 with a small grain size is extremely slow, and the impurity diffusion rate in the polycrystalline silicon layer 108 with a large grain size is fast. Therefore, the ultra-shallow junction 114 has a diffusion layer depth of 300 to 500 people and the diffusion layer depth is 0.
．． A deep junction 115 of 2 to 0.3 μm can be formed at the same time.

Incidentally, the polycrystalline silicon film 108 can also be used as an extraction electrode for the source/drain portion of a MOS transistor. In addition, although the above embodiment is an example in which N-type impurities are doped, PNP-type bipolar transistors and PNP-type bipolar transistors doped with P-type impurities and
Channel MO8) transistors can be formed in a similar manner.

Next, another embodiment of the present invention will be described with reference to FIG. This example aims at making high resistance polysilicon.

FIG. 2(a) shows a polycrystalline silicon film 201 with a small grain size that plays a role of high resistance on a silicon substrate 200.
A state in which 4,000 people are formed at desired positions with an insulating film 207 interposed therebetween is shown. After forming a suitable mask material (for example, oxide film or nitride film) 202 on the entire surface with a thickness of 1000 Å or more, ions are implanted for extraction (only in the contact area, since it is necessary to lower the resistance value). The window is opened only at the location 203 where the process is to be performed.

Next, as shown in FIG. 2(b), a polycrystalline silicon film 204 with a large grain size is grown over the entire surface, and a polycrystalline silicon film 206 is left on the electrode portion using an appropriate mask material 205, such as a resist film (see FIG. 2(b)). (C)). Finally, impurities are diffused to lower the resistance of the lead-out portion. According to the above method, the high resistance is formed of polysilicon 201, and the electrode portion is also formed of polysilicon 206. Since the electrode polysilicon 206 has a large particle size, impurities are diffused quickly throughout the electrode polysilicon 206. However, since the particle size is small in the resistive part, the diffusion speed is slow and the impurity does not diffuse over a wide area.

Therefore, as shown in Fig. 4, according to the conventional method, when heat treatment is performed at 800 to 1000°C in the post-process, impurities diffuse to the range (a), and the part that can be used as a resistor becomes the part (b).
However, according to the method of the present invention, impurities remain in the range (c) and other parts (d
) are all high resistance and can be used to obtain the same resistance, which is useful for miniaturization.

〔Effect of the invention〕

As explained above, the present invention uses two types of polycrystalline silicon with different grain sizes, thereby suppressing the increase in manufacturing steps such as ion implantation and heat treatment, and achieving a diffusion layer depth of 300 to 500 with one heat treatment. An ultra-shallow junction and a deep junction with a diffusion layer depth of 0.2 to 0.3 μm can be simultaneously and stably formed.

Further, when forming a resistor using polycrystalline silicon, a finer structure can be obtained.

[Brief explanation of the drawing]

FIGS. 1(a) to (") and FIGS. 2(a) to (c) are longitudinal sectional views relating to the main steps of one embodiment and another embodiment of the present invention, respectively, and FIGS. 3(a) and ( b) is a cross-sectional view for explaining the method of forming polycrystalline silicon of the present invention;
The figure is a sectional view for explaining the effects of another embodiment of the present invention, and FIG. 5 is a diagram for explaining the problems of the prior art. 100... Silicon substrate, 101, 207...
... Thick field oxide film, 102 ... Gate oxide film, 103 ... Gate electrode, 104.
...Insulating film, 105...Base region L10
6... Source/drain part, 107...
...Polycrystalline silicon film with large grain size, 108...
・Polycrystalline silicon film after etching, 109...
・Oxide film, 110...Emitter part, 111...
...Silicon substrate, 112...Polycrystalline silicon L113 with small grain size...Mask material, 11
4...Ultra shallow junction, 115...Deep junction, 116...Emitter electrode, 200...
・Silicon substrate, 201... Polycrystalline silicon film with small grain size, 202... Insulating film, 203...
... Electrode outlet, 204 ... Polycrystalline silicon film with large grain size, 205 ... Mask material,
206... Electrode made of polycrystalline silicon film with large grain size, 207... Insulating film, 300...
- Silicon substrate, 301...Very thin insulating film, 302...Polycrystalline silicon layer. Agent Patent Attorney Oto Uchihara Figure 1 Figure 2 ↓ ↓ ↓ ↓ ↓ ↓ ↓゛↓ Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] forming a first polycrystalline silicon layer having a first crystal grain size on a semiconductor substrate; and a second polycrystalline silicon layer having a second crystal grain size different from the first crystal grain size. A method for manufacturing a semiconductor integrated circuit device, comprising the steps of: forming a polycrystalline silicon layer; and introducing impurities into the first polycrystalline silicon layer and the second polycrystalline silicon layer.