JPH0314229B2 - - Google Patents

Info

Publication number
JPH0314229B2
JPH0314229B2 JP59207189A JP20718984A JPH0314229B2 JP H0314229 B2 JPH0314229 B2 JP H0314229B2 JP 59207189 A JP59207189 A JP 59207189A JP 20718984 A JP20718984 A JP 20718984A JP H0314229 B2 JPH0314229 B2 JP H0314229B2
Authority
JP
Japan
Prior art keywords
semiconductor device
resin
tie bar
lead
fins
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59207189A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6185847A (ja
Inventor
Yoshimasa Kudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP59207189A priority Critical patent/JPS6185847A/ja
Publication of JPS6185847A publication Critical patent/JPS6185847A/ja
Publication of JPH0314229B2 publication Critical patent/JPH0314229B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/461—Leadframes specially adapted for cooling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
JP59207189A 1984-10-04 1984-10-04 樹脂封止型半導体装置 Granted JPS6185847A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59207189A JPS6185847A (ja) 1984-10-04 1984-10-04 樹脂封止型半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59207189A JPS6185847A (ja) 1984-10-04 1984-10-04 樹脂封止型半導体装置

Publications (2)

Publication Number Publication Date
JPS6185847A JPS6185847A (ja) 1986-05-01
JPH0314229B2 true JPH0314229B2 (https=) 1991-02-26

Family

ID=16535721

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59207189A Granted JPS6185847A (ja) 1984-10-04 1984-10-04 樹脂封止型半導体装置

Country Status (1)

Country Link
JP (1) JPS6185847A (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6303985B1 (en) * 1998-11-12 2001-10-16 Micron Technology, Inc. Semiconductor lead frame and package with stiffened mounting paddle
JP2003204027A (ja) * 2002-01-09 2003-07-18 Matsushita Electric Ind Co Ltd リードフレーム及びその製造方法、樹脂封止型半導体装置及びその製造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2525815B1 (fr) * 1982-04-27 1985-08-30 Inf Milit Spatiale Aeronaut Substrat composite a haute conduction thermique et application aux boitiers de dispositifs semi-conducteurs

Also Published As

Publication number Publication date
JPS6185847A (ja) 1986-05-01

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