JPS6185847A - 樹脂封止型半導体装置 - Google Patents

樹脂封止型半導体装置

Info

Publication number
JPS6185847A
JPS6185847A JP59207189A JP20718984A JPS6185847A JP S6185847 A JPS6185847 A JP S6185847A JP 59207189 A JP59207189 A JP 59207189A JP 20718984 A JP20718984 A JP 20718984A JP S6185847 A JPS6185847 A JP S6185847A
Authority
JP
Japan
Prior art keywords
parts
semiconductor device
resin
resin molding
curving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59207189A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0314229B2 (https=
Inventor
Yoshimasa Kudo
工藤　好正
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59207189A priority Critical patent/JPS6185847A/ja
Publication of JPS6185847A publication Critical patent/JPS6185847A/ja
Publication of JPH0314229B2 publication Critical patent/JPH0314229B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/461—Leadframes specially adapted for cooling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
JP59207189A 1984-10-04 1984-10-04 樹脂封止型半導体装置 Granted JPS6185847A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59207189A JPS6185847A (ja) 1984-10-04 1984-10-04 樹脂封止型半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59207189A JPS6185847A (ja) 1984-10-04 1984-10-04 樹脂封止型半導体装置

Publications (2)

Publication Number Publication Date
JPS6185847A true JPS6185847A (ja) 1986-05-01
JPH0314229B2 JPH0314229B2 (https=) 1991-02-26

Family

ID=16535721

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59207189A Granted JPS6185847A (ja) 1984-10-04 1984-10-04 樹脂封止型半導体装置

Country Status (1)

Country Link
JP (1) JPS6185847A (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6303985B1 (en) * 1998-11-12 2001-10-16 Micron Technology, Inc. Semiconductor lead frame and package with stiffened mounting paddle
US8193091B2 (en) * 2002-01-09 2012-06-05 Panasonic Corporation Resin encapsulated semiconductor device and method for manufacturing the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58197866A (ja) * 1982-04-27 1983-11-17 トムソン‐セーエスエフ 熱伝導性の高い複合基体

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58197866A (ja) * 1982-04-27 1983-11-17 トムソン‐セーエスエフ 熱伝導性の高い複合基体

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6303985B1 (en) * 1998-11-12 2001-10-16 Micron Technology, Inc. Semiconductor lead frame and package with stiffened mounting paddle
US8193091B2 (en) * 2002-01-09 2012-06-05 Panasonic Corporation Resin encapsulated semiconductor device and method for manufacturing the same

Also Published As

Publication number Publication date
JPH0314229B2 (https=) 1991-02-26

Similar Documents

Publication Publication Date Title
US6723582B2 (en) Method of making a semiconductor package having exposed metal strap
US6157074A (en) Lead frame adapted for variable sized devices, semiconductor package with such lead frame and method for using same
US6420779B1 (en) Leadframe based chip scale package and method of producing the same
US5814877A (en) Single layer leadframe design with groundplane capability
US5646831A (en) Electrically enhanced power quad flat pack arrangement
US7781265B2 (en) DFN semiconductor package having reduced electrical resistance
US4684975A (en) Molded semiconductor package having improved heat dissipation
US20100193922A1 (en) Semiconductor chip package
JPH04291948A (ja) 半導体装置及びその製造方法及び放熱フィン
JP2000133767A (ja) 積層化半導体パッケ―ジ及びその製造方法
KR19980032479A (ko) 표면 설치 to-220 패키지 및 그의 제조 공정
US20050248041A1 (en) Electronic device with high lead density
US7566967B2 (en) Semiconductor package structure for vertical mount and method
US4278991A (en) IC Package with heat sink and minimal cross-sectional area
JPH11145362A (ja) 半導体デバイスのための露出されたリードフレーム製造におけるベンディング及びフォーミング方法
US20040262752A1 (en) Semiconductor device
US6921967B2 (en) Reinforced die pad support structure
JPS6185847A (ja) 樹脂封止型半導体装置
US20060145312A1 (en) Dual flat non-leaded semiconductor package
JPS6329413B2 (https=)
JP3920753B2 (ja) 半導体装置及びそれを組み込んだ電子装置
JPH05326796A (ja) 半導体装置用パッケージ
US7951651B2 (en) Dual flat non-leaded semiconductor package
JPH0210579B2 (https=)
JPS6217382B2 (https=)