JPH0314229B2 - - Google Patents

Info

Publication number
JPH0314229B2
JPH0314229B2 JP59207189A JP20718984A JPH0314229B2 JP H0314229 B2 JPH0314229 B2 JP H0314229B2 JP 59207189 A JP59207189 A JP 59207189A JP 20718984 A JP20718984 A JP 20718984A JP H0314229 B2 JPH0314229 B2 JP H0314229B2
Authority
JP
Japan
Prior art keywords
semiconductor device
resin
tie bar
lead
fins
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59207189A
Other languages
Japanese (ja)
Other versions
JPS6185847A (en
Inventor
Yoshimasa Kudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP59207189A priority Critical patent/JPS6185847A/en
Publication of JPS6185847A publication Critical patent/JPS6185847A/en
Publication of JPH0314229B2 publication Critical patent/JPH0314229B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49568Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【発明の詳細な説明】 [発明の技術分野] この発明は樹脂封止型半導体装置に関し、特に
従来品よりもピン数を増加させることができると
ともに放熱性能も従来品に劣ることのない改良さ
れた外囲器構造の樹脂封止型半導体装置に関する
ものである。
[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a resin-sealed semiconductor device, and in particular to a resin-sealed semiconductor device, which is improved in that the number of pins can be increased compared to conventional products, and the heat dissipation performance is not inferior to conventional products. The present invention relates to a resin-sealed semiconductor device having an envelope structure.

[発明の技術的背景] パワーIC等の発熱量の大きい半導体チツプを
樹脂封止型外囲器に封止する場合、該半導体チツ
プから発生する熱を外囲器外へ効率よく放散させ
ることが必要であり、従来、次のような二種の外
囲器構造が採用されてきた。
[Technical Background of the Invention] When a semiconductor chip that generates a large amount of heat, such as a power IC, is sealed in a resin-sealed envelope, it is necessary to efficiently dissipate the heat generated from the semiconductor chip to the outside of the envelope. Conventionally, the following two types of envelope structures have been adopted.

第一の外囲器構造はヒートシンク付きのもの
で、例えば第7図に示すように、樹脂モールド部
1の表面(上面もしくは下面)に一方の面が露出
する放熱板2を設け、該放熱板2の他方の面に接
着した半導体チツプを該樹脂モールド部1内に埋
め込んだものであり、この外囲器構造の場合リー
ド部3を具備しているリードフレームにはチツプ
取付ベツド部(アイランド)がなく、またリード
フレームと放熱板2とは別体であるとともに通常
は互いに異なる素材で構成されている。
The first envelope structure is one with a heat sink. For example, as shown in FIG. A semiconductor chip bonded to the other surface of the chip 2 is embedded in the resin molded part 1. In this envelope structure, the lead frame equipped with the lead part 3 has a chip mounting bed part (island). Moreover, the lead frame and the heat sink 2 are separate bodies and are usually made of different materials.

第二の外囲器構造はフイン付きのもので、第8
図及び第9図に示すように、半導体チツプ4が接
着されているチツプ取付ベツド部(アイランド)
5と一体に形成したフイン6を樹脂モールド部7
の側面に突出させてあり、この外囲器構造では該
チツプ取付ベツド部5とフイン6及びリード8は
共通のリードフレームに形成されている。なお、
第9図において、9は半導体チツプ4をチツプ取
付ベツド部5に接着しているはんだ層、10はボ
ンデイングワイヤである。
The second envelope structure has fins, and the eighth
As shown in FIG. 9 and FIG.
The fins 6 formed integrally with the resin mold part 7
In this envelope structure, the chip mounting bed portion 5, the fins 6, and the leads 8 are formed on a common lead frame. In addition,
In FIG. 9, 9 is a solder layer bonding the semiconductor chip 4 to the chip mounting bed portion 5, and 10 is a bonding wire.

[背景技術の問題点] 第7図のごとき放熱板2を使用する外囲器構造
においては、外付の付属部品として放熱板2が必
要になるうえ、リードフレームへの該放熱板2の
取付をカシメ加工などによつて行わなければなら
ぬため、従来のフインなし外囲器構造の半導体装
置(図示せず)にくらべて半導体装置1個あたり
の製造コストが高くなる問題点があつた。
[Problems in the Background Art] In the case of an envelope structure using the heat sink 2 as shown in FIG. 7, the heat sink 2 is required as an external accessory, and the attachment of the heat sink 2 to the lead frame is difficult. This has to be done by caulking or the like, which poses a problem in that the manufacturing cost per semiconductor device is higher than that of a conventional semiconductor device with a finless envelope structure (not shown).

一方、第8図及び第9図のごときリード部6付
きの外囲器構造を有する半導体装置には次のよう
な問題点があつた。
On the other hand, the semiconductor device having an envelope structure with lead portions 6 as shown in FIGS. 8 and 9 has the following problems.

該半導体装置を電子機器に組み込む際に樹脂
モールド部7の側面から突出しているフイン6
を該電子機器の冷却部に接続しなければならな
いので占有面積を広く要し、従つて、該半導体
装置を含む回路部品の実装密度が低くなつて電
子機器の小型化を阻害する結果となつている。
Fins 6 protruding from the side surface of the resin mold part 7 when the semiconductor device is incorporated into electronic equipment.
must be connected to the cooling section of the electronic device, which requires a large area, and as a result, the packaging density of circuit components including the semiconductor device becomes low, which impedes miniaturization of the electronic device. There is.

樹脂モールド部側面から幅広のフイン6が突
出しているため、フイン6と樹脂モールド部と
の接合面に生じるわずかな間隙を通つて該樹脂
モールド部7内に湿気が侵入しやすい構造とな
つている。
Since the wide fins 6 protrude from the side surface of the resin mold part, the structure is such that moisture easily enters into the resin mold part 7 through a small gap created at the joint surface between the fins 6 and the resin mold part. .

特に、樹脂モールド部側面に突出しているフ
イン6の根元の部分は第9図に示すようにチツ
プ取付ベツド部5と連続した同一水平面上の位
置にあるため、一旦フイン6と樹脂モールド部
との接合面に間隙が生じるとチツプ取付ベツド
部への湿気侵入経路が直線的で非常に短く、従
つて半導体チツプ4が湿気に侵されやすい構造
となつている。
In particular, since the root portion of the fin 6 protruding from the side surface of the resin mold part is located on the same horizontal plane continuous with the chip mounting bed part 5, as shown in FIG. If a gap is created in the bonding surface, the path for moisture to enter the chip mounting bed is straight and very short, so that the semiconductor chip 4 is easily attacked by moisture.

幅広のフイン6を樹脂モールド部の外周縁に
設けるとリード部8の数が少なくなり、従つて
半導体装置のピン数(外部端子の数)を減らさ
ねばならなくなるが、最近では半導体チツプに
おける素子の集積度が以前よりも高くなつてい
るため従来よりも多くのピン数を必要としてお
り、従つて該フイン6を設けることは最近の素
子の高集積化を阻害することになる。あるい
は、チツプ取付ベツド部5にフイン6を設けた
リードフレームを使用してフインのない従来品
と同じピン数の半導体装置を構成しようとすれ
ば、半導体装置の平面面積を大型化しなければ
ならないが、大型になれば電子機器等における
回路部品の実装密度が低下して該電子機器等の
小型化も阻害されることになる。
Providing wide fins 6 on the outer periphery of the resin molded portion reduces the number of lead portions 8 and therefore requires a reduction in the number of pins (the number of external terminals) of the semiconductor device. Since the degree of integration is higher than before, a larger number of pins is required than before, and therefore, providing the fins 6 hinders the high integration of recent devices. Alternatively, if a lead frame with fins 6 provided in the chip mounting bed portion 5 is used to construct a semiconductor device with the same number of pins as a conventional product without fins, the planar area of the semiconductor device must be increased. If the size of the electronic device increases, the mounting density of circuit components in the electronic device or the like will decrease, and miniaturization of the electronic device or the like will be hindered.

フイン6を設けるとともにピン数を従来の半
導体装置と同数にした場合、各リード部8の内
側端部とチツプ取付ベツド部5との間の距離を
大きくせざるを得なくなり、その結果、各リー
ド部に接続するボンデイングワイヤが長くなつ
て該ボンデイングワイヤとチツプ取付ベツド部
との接触が生じやすくなつたり、或いはボンデ
イングワイヤ相互の接触が生じやすくなる等の
問題が起こり、従つて不良品発生の確率が著し
く増大する。
If the fins 6 are provided and the number of pins is the same as in conventional semiconductor devices, the distance between the inner end of each lead portion 8 and the chip mounting bed portion 5 must be increased, and as a result, each lead As the bonding wire connected to the chip becomes longer, problems such as contact between the bonding wire and the chip mounting bed, or mutual contact between the bonding wires may occur, which increases the probability of defective products. increases significantly.

以上のように、従来の樹脂封止型半導体装置に
は種々の問題点があつた。
As described above, conventional resin-sealed semiconductor devices have had various problems.

[発明の目的] この発明の目的は、前記のごとき問題点のな
い、改良された樹脂封止型半導体装置を提供する
ことである。詳細には、樹脂モールド部の外周に
張り出したフインのない外形寸法が小型である半
導体装置を提供することであり、また外形寸法が
小型であるにもかかわらずピン数が多くとれる半
導体装置を提供することであり、さらにまた放熱
性及び耐湿性が良好であるとともにボンデイング
ワイヤに基因する不良品を生じる恐れがなく、し
かも安価なコストで製造することができる樹脂封
止型半導体装置を提供することである。
[Object of the Invention] An object of the present invention is to provide an improved resin-sealed semiconductor device that does not have the above-mentioned problems. Specifically, the object is to provide a semiconductor device with a small external dimension without fins protruding from the outer periphery of a resin molded part, and also to provide a semiconductor device with a large number of pins despite the small external dimension. Furthermore, it is an object of the present invention to provide a resin-sealed semiconductor device that has good heat dissipation properties and moisture resistance, is free from the possibility of producing defective products due to bonding wires, and can be manufactured at low cost. It is.

[発明の概要] この発明による樹脂封止型半導体装置における
特徴は、チツプ取付ベツド部の外周から突出して
いるタイバーに少なくとも一ケ所以上のU字形屈
曲部を設けるとともに該U字形屈曲部の底面を樹
脂モールド部の表面に露出させたことである。こ
のような構造によれば、タイバーが放熱板として
働くため、従来品のごときフインを設ける必要が
なくなつてピン数(リード数)を増加させること
ができると同時に放熱板を使用せずに放熱性のよ
い樹脂封止型半導体装置を安価なコストで製造す
ることができる。また、前記のごとき構造の本発
明の半導体装置では、各リード部をチツプ取付ベ
ツド部の近くに配置できるため、ボンデイングワ
イヤの長さを長くする必要がなく、従つてボンデ
イングワイヤに基因する不良品発生の確率が低
く、高歩留りで製造することができる。更に、ピ
ン数が多いので高集積度のIC等を製造すること
ができる。
[Summary of the Invention] The resin-sealed semiconductor device according to the present invention is characterized in that the tie bar protruding from the outer periphery of the chip mounting bed is provided with at least one U-shaped bent portion, and the bottom surface of the U-shaped bent portion is provided with at least one U-shaped bent portion. This is because it is exposed on the surface of the resin mold part. According to this structure, the tie bars act as heat sinks, so there is no need to provide fins like in conventional products, and the number of pins (leads) can be increased. At the same time, heat can be dissipated without using a heat sink. A resin-sealed semiconductor device with good properties can be manufactured at low cost. Furthermore, in the semiconductor device of the present invention having the above-described structure, each lead part can be placed near the chip mounting bed part, so there is no need to increase the length of the bonding wire. The probability of occurrence is low and it can be manufactured with high yield. Furthermore, since the number of pins is large, highly integrated ICs and the like can be manufactured.

[発明の実施例] 以下に第1図及び第2図を参照して本発明の一
実施例について説明する。
[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

第1図は本発明によるDIP樹脂封止型半導体装
置の樹脂封止前の状態を示した斜視図であり、同
図において5はリードフレームの一部を構成して
いるチツプ取付ベツド部、8は同じくリードフレ
ームの一部を構成しているリード部、11は同じ
くリードフレームの一部を構成するとともに該チ
ツプ取付ベツド部5の外周に突設されたタイバ
ー、9は半導体チツプ4をチツプ取付ベツド部5
に接着しているはんだ層、10は半導体チツプ4
上のボンデイングパツドとリード部8とに接続さ
れたボンデイングワイヤである。
FIG. 1 is a perspective view showing the state of the DIP resin-sealed semiconductor device according to the present invention before resin sealing. 11 is a lead portion which also constitutes a part of the lead frame; 11 is a tie bar which is also a part of the lead frame and protrudes from the outer periphery of the chip mounting bed portion 5; and 9 is a tie bar for mounting the semiconductor chip 4. Bed part 5
10 is a solder layer adhered to a semiconductor chip 4.
This is a bonding wire connected to the upper bonding pad and lead portion 8.

タイバー11の大部分は各リード部8よりも幅
広に形成されており、且つ、その先端部には幅の
狭い狭小部11bが設けられている。また、幅広
の部分にはほぼU字形の屈曲部11aが形成され
ており、該屈曲部11aの水平部分すなわちU字
形の底部は、第2図のように樹脂モールド部7を
形成した時には該樹脂モールド部7の底面(半導
体チツプ搭載面の反対面)に露出しているためタ
イバー11が放熱板として機能し、従つて従来の
フイン付き半導体装置と同様に放熱性のよい樹脂
封止型半導体装置となつている。また、タイバー
11の屈曲部11aは樹脂モールド部7の表面に
露出しているが、露出箇所は取扱い上樹脂モール
ド部との間に間隙を生じやすいようなところでな
く、また該表面から樹脂モールド部7内への湿気
の侵入は屈曲の経路をとらなければならないた
め、湿気がチツプ取付ベツド部に達する恐れは少
なく、従つてこの面からも耐湿性の高い半導体装
置となつている。
Most of the tie bar 11 is formed wider than each lead part 8, and a narrow part 11b is provided at the tip thereof. Further, a substantially U-shaped bent part 11a is formed in the wide part, and the horizontal part of the bent part 11a, that is, the bottom part of the U-shape, is formed with the resin when the resin molded part 7 is formed as shown in FIG. Since the tie bars 11 are exposed on the bottom surface of the mold part 7 (the surface opposite to the surface on which the semiconductor chip is mounted), they function as a heat dissipation plate, and therefore the resin-sealed semiconductor device has good heat dissipation properties like the conventional finned semiconductor device. It is becoming. Furthermore, although the bent portion 11a of the tie bar 11 is exposed on the surface of the resin molded portion 7, the exposed portion is not in a place where a gap is likely to be created between the resin molded portion and the resin molded portion from the surface. Since moisture must take a curved path to enter into the semiconductor device 7, there is little risk that the moisture will reach the chip mounting bed, making the semiconductor device highly moisture resistant from this point of view as well.

そのうえ、本発明の半導体装置では従来のフイ
ン付き半導体装置のごときフインがないため、該
フイン付き半導体装置よりもピン数が多くなつて
おり、多ピン型の高密度ICに好適な構造となつ
ている。
Furthermore, since the semiconductor device of the present invention does not have fins as in conventional fin-equipped semiconductor devices, the number of pins is greater than that of the conventional fin-equipped semiconductor device, and the structure is suitable for multi-pin high-density ICs. There is.

第3図は本発明の第二実施例の半導体装置の底
面図である。この実施例に示した半導体装置はフ
ラツトパツケージ型リードフレームを用いて構成
されたものである。該リードフレームのチツプ取
付ベツド部にはその各辺に第1図と同形のタイバ
ー11が突設されており、該タイバー11の各屈
曲部11aは樹脂モールド部7の底面に4か所露
出している。また、前記のごとき構造のリードフ
レームではタイバー露出部の存在にかかわらずチ
ツプ取付ベツド部の外周縁の全長にわたつてリー
ド部を密に配置することができるので(リード部
とタイバー露出部とが同一平面上にないので相互
干渉がないため)、第3図の半導体装置では樹脂
モールド部7の外周縁の全体にわたつてリード部
8が密植され、また、4本のタイバーによつて4
個の屈曲部11aが樹脂モールド部7の底面に露
出した構成となつている。
FIG. 3 is a bottom view of a semiconductor device according to a second embodiment of the present invention. The semiconductor device shown in this embodiment is constructed using a flat package lead frame. A tie bar 11 having the same shape as that shown in FIG. ing. In addition, with the lead frame having the above structure, the lead parts can be arranged closely over the entire length of the outer periphery of the chip mounting bed regardless of the existence of the exposed tie bar parts (the lead parts and the exposed tie bar parts are In the semiconductor device shown in FIG. 3, the lead parts 8 are densely planted over the entire outer periphery of the resin mold part 7, and the four tie bars
The bent portions 11a are exposed at the bottom surface of the resin molded portion 7.

第4図及び第5図は本発明の実施例を示す断面
図であり、第4図はタイバー11の屈曲部11a
を樹脂モールド部7の上面に露出させた構造の実
施例を示し、第5図はタイバー11の屈曲部11
aを樹脂モールド部7の下面に露出させた構造の
実施例を示す。また第5図はタイバー11に複数
個の屈曲部11aを形成するとともにそのうちの
一つを樹脂モールド部7の下面から突出させた実
施例を示したものである。なお、同図において第
1図と同一符号で表示されている部分は第1図に
示した部分と同一の部分を表している。
4 and 5 are cross-sectional views showing an embodiment of the present invention, and FIG. 4 shows the bent portion 11a of the tie bar 11.
FIG. 5 shows an embodiment in which the bent portion 11 of the tie bar 11
An example of a structure in which part a is exposed on the lower surface of the resin molded part 7 is shown. Further, FIG. 5 shows an embodiment in which a plurality of bent portions 11a are formed on the tie bar 11 and one of the bent portions is made to protrude from the lower surface of the resin molded portion 7. Note that in this figure, parts indicated by the same reference numerals as in FIG. 1 represent the same parts as shown in FIG. 1.

第6図のa,b,cは樹脂モールド部7の表面
に露出するタイバー屈曲部11aの平面形状の例
を示したものであり、樹脂モールド部7の表面に
露出するタイバー屈曲部の形状は第6図に示すよ
うに種々の形状であつてもよい。
6a, b, and c show examples of the planar shape of the tie bar bent portions 11a exposed on the surface of the resin molded portion 7, and the shape of the tie bar bent portions exposed on the surface of the resin molded portion 7 is as follows. As shown in FIG. 6, various shapes may be used.

[発明の効果] 以上の実施例で説明したように、本発明の半導
体装置は、 (a) 樹脂モールド部の側面にフインが突出してい
ないので小型で占有面積が小さく、従つて公知
のフイン付き半導体装置よりも高い実装密度で
電子機器等に実装することができ、電子機器の
小型化に有利である、 (b) フイン付き半導体装置よりも防湿性にすぐれ
るとともに該半導体装置に劣らない良好な放熱
性能を有している、 (c) フイン付き半導体装置よりもピン数が多く、
高密度ICに好適である、 (d) ヒートシンク付き半導体装置よりもはるかに
安価なコストで製造できる、 等の種々の利点を備えており、本発明の半導体装
置によれば従来のフイン付き半導体装置及びヒー
トシンク付き半導体装置に関する問題点が解消す
る。
[Effects of the Invention] As explained in the above embodiments, the semiconductor device of the present invention has the following advantages: (a) Since the fins do not protrude from the side surface of the resin molded part, the semiconductor device is small and occupies a small area; It can be mounted in electronic equipment, etc. with a higher packing density than semiconductor devices, and is advantageous for miniaturizing electronic equipment. (b) It has better moisture resistance than semiconductor devices with fins, and is as good as the semiconductor devices. (c) Has more pins than semiconductor devices with fins,
The semiconductor device of the present invention has various advantages such as being suitable for high-density ICs, and (d) being able to be manufactured at a much lower cost than semiconductor devices with heat sinks. And problems related to semiconductor devices with heat sinks are solved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の樹脂封止型半導体装置の樹脂
封止前の状態を示した斜視図、第2図は第1図の
半導体装置の完成状態における底面図、第3図は
本発明の他の実施例の半導体装置の底面図、第4
図及び第5図は第1図及び第2図の半導体装置の
変形実施例の断面図、第6図は第1図乃至第5図
の各実施例において樹脂モールド部の表面に露出
するタイバー屈曲部の形状を示した図、第7図は
公知のヒートシンク付き樹脂封止型半導体装置の
斜視図、第8図は公知のフイン付き樹脂封止型半
導体装置の斜視図、第9図は第8図の−矢視
断面図である。 1……樹脂モールド部、2……放熱板(ヒート
シンク)、3……リード部、4……半導体チツプ、
5……チツプ取付ベツド部、6……フイン、7…
…樹脂モールド部、8……リード部、9……はん
だ層、10……ボンデイングワイヤ、11……タ
イバー、11a……タイバー屈曲部、11b……
(タイバーの)狭小部。
FIG. 1 is a perspective view showing a resin-sealed semiconductor device of the present invention in a state before resin sealing, FIG. 2 is a bottom view of the semiconductor device of FIG. 1 in a completed state, and FIG. Bottom view of a semiconductor device of another embodiment, No. 4
5 and 5 are cross-sectional views of modified embodiments of the semiconductor device shown in FIGS. 1 and 2, and FIG. 6 shows bent tie bars exposed on the surface of the resin molded portion in each of the embodiments shown in FIGS. 1 to 5. 7 is a perspective view of a known resin-sealed semiconductor device with a heat sink, FIG. 8 is a perspective view of a known resin-sealed semiconductor device with fins, and FIG. 9 is a perspective view of a known resin-sealed semiconductor device with fins. It is a sectional view taken along the - arrow in the figure. 1... Resin mold part, 2... Heat sink (heat sink), 3... Lead part, 4... Semiconductor chip,
5... Chip mounting bed part, 6... Fin, 7...
...Resin mold part, 8... Lead part, 9... Solder layer, 10... Bonding wire, 11... Tie bar, 11a... Tie bar bent part, 11b...
Narrow part (of a tie bar).

Claims (1)

【特許請求の範囲】[Claims] 1 半導体チツプを取り付けるためのチツプ取付
ベツド部と、該チツプ取付ベツド部の外周から突
出するタイバーと、該チツプ取付ベツド部の周囲
に配置されたリード部とを有するリードフレーム
を使用し、該チツプ取付ベツド部の全部と該タイ
バーのほぼ全体と該リード部の一端側とが樹脂モ
ールド部の内に封入されている樹脂封止型半導体
装置において、該タイバーに少なくとも一ケ所以
上のU字形屈曲部を形成するとともに該U字形屈
曲部の底部を該樹脂モールド部の表面に露出させ
たことを特徴とする樹脂封止型半導体装置。
1. Using a lead frame having a chip mounting bed section for mounting a semiconductor chip, a tie bar protruding from the outer periphery of the chip mounting bed section, and a lead section disposed around the chip mounting bed section, In a resin-sealed semiconductor device in which the entire mounting bed portion, substantially the entire tie bar, and one end side of the lead portion are encapsulated within a resin mold portion, the tie bar has at least one U-shaped bent portion. 1. A resin-sealed semiconductor device characterized in that a bottom portion of the U-shaped bent portion is exposed on a surface of the resin mold portion.
JP59207189A 1984-10-04 1984-10-04 Resin-sealed semiconductor device Granted JPS6185847A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59207189A JPS6185847A (en) 1984-10-04 1984-10-04 Resin-sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59207189A JPS6185847A (en) 1984-10-04 1984-10-04 Resin-sealed semiconductor device

Publications (2)

Publication Number Publication Date
JPS6185847A JPS6185847A (en) 1986-05-01
JPH0314229B2 true JPH0314229B2 (en) 1991-02-26

Family

ID=16535721

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59207189A Granted JPS6185847A (en) 1984-10-04 1984-10-04 Resin-sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPS6185847A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6303985B1 (en) * 1998-11-12 2001-10-16 Micron Technology, Inc. Semiconductor lead frame and package with stiffened mounting paddle
JP2003204027A (en) * 2002-01-09 2003-07-18 Matsushita Electric Ind Co Ltd Lead frame and its manufacturing method, resin sealed semiconductor device and its manufacturing method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58197866A (en) * 1982-04-27 1983-11-17 トムソン‐セーエスエフ Composite substrate with high thermal conductivity

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58197866A (en) * 1982-04-27 1983-11-17 トムソン‐セーエスエフ Composite substrate with high thermal conductivity

Also Published As

Publication number Publication date
JPS6185847A (en) 1986-05-01

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