JPH02192150A - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JPH02192150A JPH02192150A JP976589A JP976589A JPH02192150A JP H02192150 A JPH02192150 A JP H02192150A JP 976589 A JP976589 A JP 976589A JP 976589 A JP976589 A JP 976589A JP H02192150 A JPH02192150 A JP H02192150A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- lead
- parts
- lead frame
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000005530 etching Methods 0.000 claims description 4
- 229920005989 resin Polymers 0.000 abstract description 21
- 239000011347 resin Substances 0.000 abstract description 21
- 238000007789 sealing Methods 0.000 abstract description 13
- 238000001721 transfer moulding Methods 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 4
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 230000017525 heat dissipation Effects 0.000 description 8
- 238000005452 bending Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 229910000906 Bronze Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000010974 bronze Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は樹脂封止型半導体装Ｉｔ、特に、リードフレー
ムのインナーリード部とアウターリード部との板厚に差
異を設けた熱抵抗を低減できる半導体装置に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a resin-sealed semiconductor device It, in particular, to reduce thermal resistance by providing a difference in thickness between an inner lead portion and an outer lead portion of a lead frame. This article relates to semiconductor devices that can be used.
樹脂封止型半導体装置の製造に際し、リードフレームが
使用される。当該リードフレームの素材は一般に金属材
料よりなり、例えは金属板をプレス加工またはエツチン
グ加工して製造される。Lead frames are used when manufacturing resin-sealed semiconductor devices. The lead frame is generally made of a metal material, and is manufactured, for example, by pressing or etching a metal plate.
リードフレームの主要構成は、その中央に半導体チップ
を固着させるタブ部と該タブ部の周辺に多数配設された
リード部とこれら各リード部を連結しているタイバ一部
とフレーム（枠）部とより成る。The main components of a lead frame are a tab part in the center that fixes the semiconductor chip, a large number of lead parts arranged around the tab part, a part of tie bar and a frame part that connect these lead parts. It consists of
樹脂封止型半導体装置の製造に際Ｅ７ては、尚該リード
フレームのタブ部に半導体チップを固着し、当該チップ
のポンディングパッドとリード部とをコネクタワイヤに
よりワイヤボンデインクして電気的に接快後に、トラン
スファーモールドにより樹脂封止を行々うという主要工
程を経て製造される。In E7, when manufacturing a resin-sealed semiconductor device, a semiconductor chip is fixed to the tab portion of the lead frame, and the bonding pad of the chip and the lead portion are wire bonded using a connector wire to electrically connect the semiconductor chip to the tab portion of the lead frame. After being in contact with the public, it is manufactured through the main process of resin sealing using transfer molding.
当該樹脂封止により形成される樹脂封止体の内部に埋設
されるリード部はインナーリード部と称され、一方、当
該樹脂封止体の外部に露出され外部接続端子として使用
されるリード部はアウターリード部と称さｔている。The lead part buried inside the resin sealing body formed by the resin sealing is called an inner lead part, while the lead part exposed outside the resin sealing body and used as an external connection terminal is called an inner lead part. It is called the outer lead section.
従来、かかるリードフレームのインナーリード部とアウ
ターリード部とは、一般にそれらの板厚は均一である。Conventionally, the inner lead portion and the outer lead portion of such a lead frame generally have uniform thickness.
もっとも、当該リードフレームの板厚に差異を設けた半
導体装置について述べた特許の例としては、本出願人に
係る特開昭５９−９８５４７号公報が挙げられる。また
、リードフレームの板厚自体に差異を設けたものではな
いが、インナーリード部に侵入防止部材を突設してなる
半導体装ｔＫついて述べた特許の例として、本出願人に
係る発明隘８４００５６１が挙げられる。However, an example of a patent describing a semiconductor device in which lead frames have different plate thicknesses is Japanese Patent Laid-Open No. 1988-98547, filed by the present applicant. In addition, as an example of a patent that describes a semiconductor device tK in which an intrusion prevention member is provided protruding from the inner lead part, although there is no difference in the plate thickness of the lead frame itself, Invention No. 8400561 of the present applicant is cited. can be mentioned.
しかるに、上記の如く、インナーリード部とアウターリ
ード部との板厚を均一にした樹脂制止型そこで、タブ部
を下方向に伸長させて、当該タブ部の下面［７で樹脂封
止体を形成して、半纏体チップからの発熱を当該タブ部
を介して放散（放熱）させたり、あるいは、半導体チッ
プの上部に放熱体（金属体）をその半分を樹脂封止体内
部に埋設（７他の半分を樹脂封止体外部に露出させて放
熱を良好にするとかの対策がとられているが、前者は耐
湿性を劣化させ、また、後者は半導体装置（パッケージ
）の外形を変更し、パッケージをプリント配線基板に実
装するときに実装密度を低下させたりする。However, as described above, in the resin-sealed type in which the thickness of the inner lead part and the outer lead part are made uniform, the tab part is extended downward to form a resin-sealed body on the lower surface [7] of the tab part. Then, the heat generated from the semi-integrated chip is dissipated (heat radiated) through the tab part, or half of the heat dissipating body (metal body) is buried on the top of the semiconductor chip inside the resin sealing body (7 etc.). Measures have been taken to improve heat dissipation by exposing half of the resin encapsulation to the outside, but the former deteriorates moisture resistance, and the latter requires changing the external shape of the semiconductor device (package). When mounting a package on a printed wiring board, the mounting density is reduced.
普だ、パッケージの放熱性を補なうために、当該実装用
基板に放熱性の良いものを選択したりして放熱対策をと
ることがある。Usually, in order to compensate for the heat dissipation of the package, heat dissipation measures are taken, such as by selecting a mounting board with good heat dissipation.
尚前記でリードフレームの板厚に差異を設けた半導体装
置の特許の例と（，７て挙けた特開昭５９９８５４７号
公報は、リードフレームのインナーリード部をアウター
リード部よりも薄くして、インナーリード部の配線パタ
ーンの微細加工を可能にすることを主目的としたもので
、半導体装置の熱抵抗の低減を目的としたものではない
。In addition, in the above-mentioned example of a patent for a semiconductor device in which the plate thickness of the lead frame is made different, and in Japanese Patent Application Laid-Open No. 5998547 cited in (7), the inner lead part of the lead frame is made thinner than the outer lead part, The main purpose is to enable fine processing of the wiring pattern of the inner lead part, and is not intended to reduce the thermal resistance of the semiconductor device.
また、発明Ｎｎ８４００５６１けインナーリード部に侵
入防止部材を突設し７て、耐湿性を向上させようとした
もので、同様に熱抵抗の低減を目的としたものではない
。Further, the invention No. 8400561 is intended to improve moisture resistance by protruding an intrusion prevention member from the inner lead portion, and is not intended to similarly reduce thermal resistance.
本発明は、上記の如きリードフレームを用いた場合の熱
抵抗″’＆低減することを目的と１２だもので、それも
、放熱体を埋設する必要がなく、１だ、パッケージの外
形を変更することなく、さらに、実装密度に影響を与え
ることなく熱抵抗を低減できる技術を提供することを目
的とする。The present invention aims to reduce the thermal resistance when using a lead frame such as the one described above.It also eliminates the need to embed a heat dissipation body, and 1) changes the external shape of the package. The purpose of the present invention is to provide a technology that can reduce thermal resistance without affecting packaging density.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細薔の記述および飾付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the attached drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
本発明でｆｄ：、リードフレームのインナーリードた。In the present invention, fd: is the inner lead of the lead frame.
これにより、インナーリード部の樹脂封止体との接触面
績が増え、パッケージ内に発生する熱が、インナーリー
ド部とアウターリート部との板厚を均一にしている場合
に比較（７て、放熱され易くなり、熱抵抗を低減できる
。As a result, the contact area of the inner lead part with the resin sealing body increases, and the heat generated in the package is reduced compared to when the thickness of the inner lead part and the outer lead part are made uniform (7. Heat is dissipated more easily and thermal resistance can be reduced.
インナーリード部のみがアクタ−リード部よりもその板
厚が厚いたけで、樹脂封止体の外部に露出しているアウ
ターリード部の板厚には影響なく、従来と同様に実装で
きるし、パッケージ内部に放熱体を埋設したりしないの
でパッケージ外形も従来と同様のものとなすことができ
る。従って、実装密度の低下を防止できる。Only the inner lead part is thicker than the actor lead part, so the thickness of the outer lead part exposed outside the resin molding body is not affected, and it can be mounted in the same way as before, and the package can be mounted in the same way as before. Since no heat dissipation body is buried inside, the package external shape can be the same as the conventional one. Therefore, a reduction in packaging density can be prevented.
パッケージ自体の放熱性が良くなるので、実装用基板に
特に放熱性の艮いものを選択しなくても済む。Since the heat dissipation of the package itself is improved, there is no need to select a mounting board with special heat dissipation properties.
また、インナーリード部の板厚が庫〈なったので、トラ
ンスファーモールド時のレジン流れによるインナーリー
トの曲りも少なくなる。Also, since the thickness of the inner lead part is reduced, bending of the inner lead due to resin flow during transfer molding is reduced.
次に、本発明の実施例を図面に基づいて説明する。 Next, embodiments of the present invention will be described based on the drawings.
第１図は本発明の実施例を示す半導体装置の要部断面図
、第２図は同半導体装置の斜視図を示す。FIG. 1 is a sectional view of a main part of a semiconductor device showing an embodiment of the present invention, and FIG. 2 is a perspective view of the same semiconductor device.
尚第１図は、第２図Ａ−Ａ’線に沿う断面で示しである
。Note that FIG. 1 is a cross section taken along the line AA' in FIG. 2.
当該実施例における半導体装置は、Ｊベンド（ｂｅｎｄ
）タイプの半導体パッケージ（ＳＯＪ）を例示しである
。The semiconductor device in this example has a J-bend (bend)
) type semiconductor package (SOJ) is exemplified.
リードフレーム１のタブ部２には半導体チップ３が固着
されている。A semiconductor chip 3 is fixed to a tab portion 2 of a lead frame 1.
半導体チップ３は、コネクタ用ワイヤ４により、リード
フレーム１のインナーリード部５と電気的に接続されて
いる。The semiconductor chip 3 is electrically connected to the inner lead portion 5 of the lead frame 1 by a connector wire 4 .
樹脂封止体６の外部には、リードフレーム１のアウター
リード部７が露出しており、当該アウターリード部７は
樹脂封止体６の底面に折曲げられている。Outer lead portions 7 of the lead frame 1 are exposed outside the resin sealing body 6 , and the outer lead portions 7 are bent onto the bottom surface of the resin sealing body 6 .
なお、第１図にて、８けリードフレームのタイバ一部を
示す。In addition, in FIG. 1, a part of the tie bar of the 8-digit lead frame is shown.
第１因に示すように、インナーリート部５の板厚は、ア
ウターリード部７の板厚よりも厚く構成されている。As shown in the first factor, the thickness of the inner lead portion 5 is configured to be thicker than the thickness of the outer lead portion 7.
当該リードフレーム１ハ、１り１」メけ、コノく−ル。The lead frame 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, and 1, respectively, respectively.
４２アロイなどの鉄系相料またにリン青銅などの銅系材
料によりｆｋｉ成されている。The fki is made of an iron-based phase material such as 42 alloy or a copper-based material such as phosphor bronze.
当該リードフレーム１は、段エツテンクノ用工により、
インナーリート部５をアウターリードｓ７よりも厚くす
ることにより形成することかできる。The lead frame 1 is manufactured by the following steps:
It can be formed by making the inner lead portion 5 thicker than the outer lead s7.
エツチング加工は、例えはノズルを用いて塩化第２鉄な
どの溶液よりなるエツチング液をリードフレーム素材の
金属板に噴射する方法により行うことができる。The etching process can be performed, for example, by using a nozzle to spray an etching liquid made of a solution of ferric chloride or the like onto the metal plate of the lead frame material.
・しＩＩえは、アウターリード部７の板厚か０．２ ｍ
ｍと１、たらインターリード部５の板厚を０．４ ｍｍ
と厚くする０
半畳体チップ３は、例えはシリコン単結晶基板から成り
、周知の政術によってこのチップ内Ｋｌｄ多数の回路素
子が形成され、１つの回路機能が与えられている。回路
素子の具体例は、例えばＩＶＩＯＳトランジスタから成
り、こｈらの回路素子によって、例えは論理回路および
メモリの回路機能が形成されている。・The thickness of the outer lead part 7 is 0.2 m.
m and 1, the plate thickness of the cod interlead part 5 is 0.4 mm
The semicircular chip 3 is made of, for example, a silicon single crystal substrate, and a large number of circuit elements are formed within this chip using well-known political techniques to provide one circuit function. A concrete example of the circuit elements is, for example, an IVIOS transistor, and these circuit elements form the circuit functions of, for example, a logic circuit and a memory.
コネクタ用ワイヤ４には、世」えは、Ａ ｕ ？Ｉｓが
使用される。The connector wire 4 has an A u ? Is is used.
樹脂封止は、エポキシ樹脂などのレジンを主体とした封
止材を用い、例えば、トランスファーモールド金型に、
ワイヤボンデインク後の組立品全入れ、トランスファー
モールドすることにより行うことができる。Resin sealing uses a sealing material based on resin such as epoxy resin, for example, in a transfer mold mold.
This can be done by placing the entire assembly after wire bonding ink and transfer molding.
本発明によれば、リードフレームｌのインナーリード部
５の板厚をアウターリード部７の板厚よりも厚くしたの
で、樹脂封止体６内部の熱がインナーリード部５を伝わ
って外部に放熱され易くなり、樹脂封止型半導体装置の
熱抵抗が低減され、その信頼性が向上するとともに、ア
ウターリード部７や樹脂封止体６を含むパッケージ全体
の外形には変化を生じさせずに熱抵抗を低減でき、また
、インナーリード部５の板厚が厚くなる結果、トランス
ファーモールド時のレジン流れによるインナーリード曲
りを防止できた。According to the present invention, since the thickness of the inner lead portion 5 of the lead frame l is made thicker than the thickness of the outer lead portion 7, the heat inside the resin sealing body 6 is transmitted through the inner lead portion 5 and radiated to the outside. This reduces the thermal resistance of the resin-sealed semiconductor device and improves its reliability. As a result of reducing the resistance and increasing the thickness of the inner lead portion 5, it was possible to prevent the inner lead from bending due to resin flow during transfer molding.
以上本発明者よってなさねた発明を実施例にもとづき具
体的に説明し７たか、本発明は上記実施例ＶＣ限定され
るものではなく、ぞの安旨を逸脱しない範囲で楯々変更
ｉＪ能であることはいうまでもないＯ
本発明はＳＯＪの他、フラットパックパッケージ（Ｆ
Ｆ Ｐ ）やプーアルインラインパッケージ（ＤＩＬＰ
）などの容積の樹脂封止型半導体装置に適用することが
できる。The invention which has not been made by the present inventor has been specifically explained based on the examples, but the present invention is not limited to the above-mentioned embodiments, and can be modified from time to time without departing from the spirit of the invention. Needless to say, the present invention is applicable to flat pack packages (F) in addition to SOJ.
F P ) and Pu'er Inline Package (DILP)
) and other resin-sealed semiconductor devices.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれは、下記のとおりであ
る。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
本発明によれは熱抵抗が低減され、インナーリードの樹
１旨封止の際のレジン流れによる曲りを防止することが
できた。According to the present invention, thermal resistance was reduced, and bending due to resin flow during sealing of the inner lead could be prevented.
第１図は本発明の実施例を示す半導体装置の景部所面図
、
第２図は本発明の実施例を示す半導体装置の斜視図であ
る。
１・・・リードフレーム、２・・・タブ部、３・・・半
導体チップ、４・・・コネクタ用ワイヤ、５・・・イン
ナーリード部、６・・・樹脂封止体、７・・・アウター
リード部、８・・・タイバ一部。FIG. 1 is a perspective view of a semiconductor device showing an embodiment of the invention, and FIG. 2 is a perspective view of a semiconductor device showing an embodiment of the invention. DESCRIPTION OF SYMBOLS 1... Lead frame, 2... Tab part, 3... Semiconductor chip, 4... Wire for connector, 5... Inner lead part, 6... Resin sealing body, 7... Outer lead part, 8...part of tie bar.
Claims (1)
せ、当該半導体チップとリードフレームとを電気的に接
続し、樹脂封止を行なってなる樹脂封止型半導体装置に
おいて、前記リードフレームの樹脂封止体内部のインナ
ーリード部の厚みを、当該リードフレームの樹脂封止体
外部のアウターリード部の厚みよりも厚く構成して成る
ことを特徴とする樹脂封止型半導体装置。 ２、リードフレームが、エッチング加工により形成され
、かつ、インナーリード部の板厚をアウターリード部の
板厚よりも厚く形成してなる、請求項１に記載の樹脂封
止型半導体装置。[Claims] 1. In a resin-sealed semiconductor device in which a semiconductor chip is fixed on a tab portion of a lead frame, the semiconductor chip and the lead frame are electrically connected, and resin-sealed, A resin-sealed semiconductor device characterized in that the thickness of the inner lead portion inside the resin-sealed body of the lead frame is thicker than the thickness of the outer lead portion outside the resin-sealed body of the lead frame. . 2. The resin-sealed semiconductor device according to claim 1, wherein the lead frame is formed by etching, and the inner lead portion is thicker than the outer lead portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP976589A JPH02192150A (en) | 1989-01-20 | 1989-01-20 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP976589A JPH02192150A (en) | 1989-01-20 | 1989-01-20 | Resin-sealed semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02192150A true JPH02192150A (en) | 1990-07-27 |
Family
ID=11729364
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP976589A Pending JPH02192150A (en) | 1989-01-20 | 1989-01-20 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02192150A (en) |
-
1989
- 1989-01-20 JP JP976589A patent/JPH02192150A/en active Pending
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