JPH0312100A - Method of writing test data to recording element and recording-element testing circuit - Google Patents

Abstract

PURPOSE: To improve data writing speed by conducting a MOS transistor without going through an input/output line and imparting a load directly to one bit line only. CONSTITUTION: A circuit for testing a recording element is controlled by a control circuit 1. One MOS transistor is selected from plural MOS transistors M1-M4 connecting to a pair of bit lines 2, 3 on which data consisting of binary codes propagate. A load for data is directly imparted to one bit line through the MOS transistor thus selected. The data is stored by being transferred directly to a capacitor inside a memory cell 5 connecting to the bit line to which the load is imparted. Thus, the load for data is directly transferred to the capacitor inside the memory cell and stored, therefore, time for a RAM test can be shortened.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a recording element, and in particular, to significantly reduce the time required for a RAM test on a highly densely integrated recording element, such as a RAM. The present invention relates to a method for writing test data to a recording element that can be used to write test data to a recording element, and a recording element test circuit for implementing this method.

(Prior Art) Conventionally, in the manufacture of recording elements, various strict manufacturing controls have been required in response to an increase in the degree of integration of recording elements.

For example, during the manufacturing process of the recording element, it is necessary to prevent dust and contaminants from adhering to the recording element.

However, as the degree of integration of recording elements increases, dust and contaminants tend to adhere to the recording elements, so it is inevitable that the defective rate of recording elements will increase.

Therefore, a circuit capable of performing a quality test of the recording element, that is, a RAM test, is provided inside the recording element, and the RAM test is performed on the manufactured recording element.

(Problem to be Solved by the Invention) However, in the above-mentioned test method of performing a RAM test of a recording element using a circuit within the recording element, the higher the degree of integration of the recording element, the longer the RAM test takes. It had the disadvantage of being long.

The reason for this is that in conventional RAM tests, a predetermined group of bits, for example 4 bits, 8 bits, or 16 bits, is performed in batches, and the test data is passed through the input/output line built into the RAM to be tested. This is because the data is written to the RAM, then read from the RAM, and the written and read data are compared to check for differences, thereby inspecting the quality of the RAM.

In this case, the time required for the RAM test increases in proportion to the value obtained by dividing the RAM integration degree by the bit group unit, that is, the integration degree/bit group unit.

SUMMARY OF THE INVENTION The present invention aims to solve the above-mentioned problems of the prior art, and its purpose is to provide a method of writing test data to a recording element that can significantly shorten the time required for a RAM test.

Another object of the present invention is to provide a recording element test circuit useful for carrying out the above-described method of writing test data to a recording element.

[Configuration of the Invention (Means for Solving the Problems) To solve the above problems, the method of writing test data to a recording element according to claim (1) of the present invention provides a method for writing test data into a recording element in which data consisting of a binary code is propagated. Multiple MOs connected to the bit lines of
One MoS transistor is selected from the S transistors, and a charge serving as the data is directly applied to one bit line through the selected MOS transistor, and the charge is transferred to a capacitor in a memory cell connected to the bit line to which the charge is applied. The device is characterized in that the charge serving as the data is directly transferred and held.

Further, the method of writing test data to a recording element according to claim (2) selects at least one MOS transistor from a plurality of MOS transistors connected to a pair of bit lines through which data consisting of double codes is propagated; M that was done
A charge serving as the data is directly applied to only one bit line via an OS transistor, the other bit line is held at zero potential, and the potential difference between the pair of bit lines is amplified by a sense amplifier connected to the bit line. The charge amplified by the sense amplifier is transferred to and held in a capacitor in a memory cell connected to a charged bit line.

Furthermore, the recording element test circuit according to claim (3) includes a sense amplifier that amplifies the potential of a pair of bit lines through which charges serving as data of a double code propagate, and a sense amplifier that amplifies the potential of a pair of bit lines through which charges serving as data of a double code are propagated; The charge that becomes the data is applied to only one bit line directly or through a memory cell that absorbs and holds the signal after amplification by the sense amplifier and a MOS transistor that is directly connected to each bit line. data writing means for transferring the data from the bit line to the memory cell and writing the data into the memory cell; and reading the write data written by the means and determining whether or not the read data matches the write data. A MOS including a plurality of data testing means to be tested in parallel and forming the data writing means.
The present invention is characterized in that it includes a control circuit that controls the operation of the transistor and transmits a test signal to the data test means.

Here, the MOS transistors of the data writing means include a PMOS transistor connected to a power supply and a NMMOS transistor grounded.
It is characterized by consisting of an OS transistor.

Further, the test signal transmitted from the control circuit is composed of a first test signal and a second test signal having different potential levels, and the data test means inputs the potential of one bit line to the gate side and adjusts the potential to the above potential. According to the first
A first NMOS transistor that conducts a test signal, a second NMOS transistor that inputs the potential of the other bit line to its gate side and conducts the second test signal according to the potential, and the first NMOS transistor or the second NMOS transistor. It is characterized by comprising a third NMOS transistor which inputs one of the output test signals to the gate side and becomes conductive when the read data does not match the write data.

(Function) In the method for writing test data to a recording element according to claim (1) of the present invention, a MoS transistor connected to a power supply is made conductive to directly charge only one bit line without using an input/output line. This charge is then directly transferred and held in a capacitor in a specific memory cell connected to the bit line without being amplified by a sense amplifier.

Therefore, data can be written and held in the memory cell by regarding the presence or absence of charge held in the capacitor as data of the double code PA0°, "1". Furthermore, data can be written quickly because it does not go through input/output lines.

Further, in the method of writing test data to a recording element according to claim (2), without using input/output lines, a MOS transistor connected to a power supply is made conductive to apply charge to one bit line, and the other bit line is charged. The bit line is maintained at zero potential, or the grounded MOS transistor is made conductive to bring the bit line to zero potential.Next, the potential difference between the pair of bit lines is amplified by a sense amplifier, and then the specified bit line is connected to the charged bit line. The charge is transferred to and held in the capacitor in the memory cell.

Therefore, similarly to the method for writing test data to a recording element according to claim (1), data can be quickly written and held in a memory cell. Furthermore, since the potential of the bit line is amplified by the sense amplifier, the charge is reliably transferred to and held in the capacitor in the memory cell.

Furthermore, in the recording element test circuit of claim (3), when writing data, a PMOS transistor connected to a power supply is made conductive to one bit line of the pair of bit lines to apply a charge that becomes data, and the other bit line is is maintained at zero potential, or the grounded NMOS transistor is made conductive to change the bit line to zero potential. Next, after the potential difference between the pair of bit lines is amplified by a sense amplifier, or without using a sense amplifier, the charge is directly transferred to and held in a capacitor in a specific memory cell connected to the charged bit line.

Therefore, data consisting of a binary code can be written and held in a memory cell corresponding to a 1-bit recording unit of a highly densely integrated recording element.

Then, when reading data, the charge held in the capacitor recharges the bit line by the signal from the word line, so that only one bit line has a potential.

Then, the first NMOS transistor or the second NMOS transistor
Only one of the S transistors receives an H level signal from the bit line, becomes conductive, passes only one test signal from the control circuit, and the passed test signal is transferred to the third NM.
This becomes a gate signal to the OS transistor.

Here, the potential level (H
If the data read operation is normal, the NMOS transistor that is connected to one bit line and conducts to be recharged correctly receives an L level test signal from the control circuit. It is set. Therefore, the gate signal to the third NMOS transistor becomes L level, and the third NMOS transistor is not conductive.

If the data read operation is erroneous, the NMOS transistor connected to the other bit line that is erroneously recharged and turned on will receive an H-level test signal from the control circuit. Therefore, the gate signal to the third NMOS transistor becomes H level, and the third NMOS transistor becomes conductive.

Therefore, whether the read operation (or not) is normal or not, that is, the RA
Since the third NMOS transistor is rendered non-conductive or conductive depending on whether or not a particular recording unit portion to be inspected of the recording element to be tested is normal, malfunction of the recording element can be determined.

Further, by providing a plurality of data writing means and a plurality of data reading means in parallel, it is possible to simultaneously test a plurality of recording units of a recording element that is a RAM test target.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a recording element test circuit for carrying out a method of writing test data to a recording element according to an embodiment of the present invention.

In the figure, the recording element test circuit includes a control circuit 1 that controls the operation of this circuit, and a node A from the circuit 1.
A bit line potential setting section 4 which is controlled via bit line B, C1 and D and sets the potential of the bit line 2.3 as data consisting of a binary code, and data by recording the potential set by the setting section 4. The memory cell 5 to which is written, the sense amplifier 6 that amplifies the potential of the bit line 2.3 set by the bit line potential setting unit 4, and the read data obtained by reading the data written to the memory cell 5 are connected to a node. A test circuit 7 that tests whether it is correct or not using a test signal transmitted from the control circuit 1 via E and F, a bit line 2, and an input/output line (Ilo).
8 connection or bit line 3 and input/output line (Il
o) Consists of a selection unit 10 that selects 9 connections.

Here, the control circuit 1 inputs input data DIN, which is test data consisting of binary codes, and outputs status signals to nodes A, B, C1, and D according to the input data when the data is input. Node E when reading data from memory cell 5.

Outputs a test signal to F.

The bit line potential setting unit 4 includes a PMOS transistor M1 and an NMOS transistor M2 connected to the bit line 2, and a PMOS transistor M3 and an NMOS transistor M4 connected to the bit line 3. A node A, a node B, a node C1, and a node D are connected to the gate sides of the PMOS transistor M1, NMOS transistor M2, PMOS transistor M3, and NMOS transistor M4, respectively, and the PMOS transistors M1 and M3 are connected to a power supply with a Vcc potential. The bit line 2 or 3 is maintained at Vcc potential. Further, the NMOS transistors M2 and M4 are grounded to keep the bit line 2 or 3 at zero potential.

The memory cell 5 is formed by connecting an NMOS transistor 11 and a capacitor C1 in series.
A word line W/L is connected to the gate side of the word line W/L, and charges are exchanged between the bit line 2 and the capacitor C1 in response to a signal from the word line W/L.

The test circuit 7 includes NMOS transistors M5, M6, M7,
and M8. The gate side of the NMOS transistor M5 is connected to the bit line 3, and the gate side is connected to the bit line 3.
The signal of node F is transmitted to node H according to the potential of node F. N
The gate side of the MOS transistor M6 is connected to the bit line 2, and transmits the signal of the node E to the node H according to the potential of the bit line 2. The gate side of the NMOS transistor M7 is connected to the reset line R/L, and the node H is reset to zero potential in response to a reset signal from the reset line R/L.

The gate side of the NMOS transistor M8 is connected to the node H, and the potential of the error generation line TQ is set to zero potential according to the potential of the node H.

The selection unit 10 is constructed by connecting NMOS transistors M9 and M9 and their gates to the column line COL, respectively. NMOS transistor M9 is connected to column line COL
The input line 8 and the bit line 2 are made conductive in response to a column selection signal from the input line 8 and the bit line 2.

NMOS transistor MIO conducts input line 9 and bit line 3 in response to a column signal from column line COL.

Although not shown, the bit line 2.3, bit line potential setting unit 4, memory cell 5, sense amplifier 6,
A large number of data writing and reading circuits including the test circuit 7 and the selection section 8 are connected in parallel and receive control from the control circuit 1 in parallel.

Further, each of the data writing and reading circuits has a word line W/L, a reset line R/L, and an error generation line TQ as common lines.

The general operation of the recording element test circuit will be explained based on the above configuration.

The operation is similar to that of a conventional DRAM element, and the MOS transistors M1 to M4 are rendered non-conductive under control from the control circuit 1.

In the above state, the NMOS transistors M9 to M
IO is made conductive by a column selection signal from the column line, and the input/output lines 8 and 9 are electrically connected to the bit line 2.3 and the sense amplifier 6.

Next, the sense amplifier 6 connects the capacitor C of the memory cell 5 selected by the word line W/L via the bit line 2 or 3 selected by the column selection signal.
1 is charged through the NMOS transistor Mll.

In this way, the double code "0°",
A charge corresponding to 1° of data is applied, and data is written.

Next, when reading data, the memory cell 5 receives a signal from the word line W'/L, and the NMOS transistor Mll becomes conductive, and the charge stored in the capacitor C1 is discharged to the bit lines 2 and 3. Then, the sense amplifier 6 detects and amplifies the potential change of the bit lines 2 and 3 as a state signal.Then, the amplified state signal is outputted to the electrically connected input/output lines 8 and 9.

Such operation is the same as that of a normal DRAM device.

Next, regarding the RAM test, the operation of the recording element test circuit when executing a method of writing test data to a recording element, which is an embodiment of the present invention, will be described.

Here, the RAM test is to write test data to the RAM to be tested, and then compare the data read from the RAM with the data written to the RAM.

In this embodiment, there are two types of methods for writing test data in such a RAM test. That is, one is a method that does not use the sense amplifier 6, and the other is a method that uses the sense amplifier 6.

In addition, regardless of the above-mentioned method, in this example, NMO5
Transistors M9 and MIO become non-conductive and the input/output line 8.9 is cut off from the bit line 2.3. That is,
Input/output lines 8.9 are not used.

First, a method that does not use the sense amplifier 6 will be explained.

The test data DIN is a double code (“0”° and '1
), the test data of "1" is directly applied to the capacitor C1 of the memory cell 5 via the bit line 2 during the data write operation. That is, it is connected to the bit line 2. After the word line W/1° having the memory cell 5 is selected, the control circuit 1 maintains the node A at L level to turn on the PMO8 transistor M1, and the bit line 2 becomes the potential Vcc.

At this time, NM selected by the word line W/L
The OS transistor Mll becomes conductive, and the capacitor C1 is directly charged without using the sense amplifier 6. This charging corresponds to writing data "1". At this time, test data ``1''' applied to bit line 2
The same data is latched in the control circuit 1, and when reading the data, the write data is transferred to nodes E and F.
Output to.

Next, a method using the sense amplifier 6 will be explained.

Similar to the method that does not use the sense amplifier 6, when 1° is selected as the test data, the control circuit 1 maintains the node A at the L level and the node D at the H level, and PM
The OS transistor M1 and the NMOS transistor M4 are made conductive. Then, the bit line 2 becomes potential Vcc, and the bit line 3 becomes zero potential.Then, the sense amplifier 6 detects and amplifies the potential difference between the bit line 2 and the bit line 3. Similarly, the selected capacitor C1 is charged to the Vcc potential. In this way, data ゛1゛.

is written into the memory cell 5.

Next, the operation of reading data written into the memory cell 5 by either of the two data writing methods described above and comparing the read data with the written data will be described.

First, the control circuit 1 connects nodes A and C to an H level.
MOS transistors M1 to M
4 becomes non-conductive.

Transistor Mll is then turned on by the signal from word line 2, and the charge held in capacitor C1 is discharged to word line 2. Then, the sense amplifier 6 detects that the bit line 2 is at the H level while the bit line 3 is at zero potential, that is, at the L level.

Control circuit 1 maintains node E and node F at L level until the above-described detection by sense amplifier 6 is performed. When the above detection is performed, the control circuit 1 outputs a test signal corresponding to the latched test data via the nodes E and F when the control circuit 1 does not output the status signal via the nodes A to F. That is, since the test data is 1°, the control circuit 1 outputs an L-level test signal to the node E and an H-level test signal to the node F, and the data "1" written in the memory cell 5 is not tested. Tested in circuit 7.

That is, the L level (zero potential) signal on bit line 3 is NM
The signal is transmitted to the gate side of the OS transistor M5, and the H level signal on the bit line 2 is transmitted to the gate side of the NMOS transistor M6. Then, NMOS transistor M
5 becomes non-conductive, NMOS transistor M6 becomes conductive, the L-level test signal of node E is transmitted to node H, and NMOS transistor M8 remains non-conductive.

Therefore, the error generation line TQ, which is previously charged and at H level, maintains the H level during the read operation of the RAM test. This means that the data read from the capacitor C1 matches the data written to the capacitor C1 of the memory cell 5.

Therefore, it can be confirmed that the recording element that is the subject of the RAM test is normal.

Next, if an error occurs when reading the data written in the memory cell 5 and data 0 is read when data 1 is supposed to be read, the sense amplifier 6
detects that bit line 3 is at H level while bit line 2 is at zero potential, that is, at L level. Therefore, the NMOS transistor M6 inputs a zero potential to its gate side and becomes non-conductive, whereas the NMOS transistor M5 inputs an H level to its gate side and becomes conductive.

Then, the test signal at the H level of the node F is transmitted to the node H, and the NMOS transistor M8 becomes conductive. Therefore, the error generation line TQ, which has been charged in advance and is at H level, becomes NMO during the read operation of the RAM test.
It is discharged to the ground through the S transistor M8 and becomes zero potential. This means that the data read from the capacitor C1 does not match the data written to the capacitor C1 of the memory cell 5.

Therefore, it can be confirmed that the recording element that is the subject of the RAM test is defective.

In this way, although not shown, the error generation line TQ is a common line that connects in parallel all the NMo5 transistors M8 installed in each of the other recording element test circuits installed in parallel, so that for each memory cell = The data to be sold is simultaneously processed in parallel by the test circuit, and the processing results are transmitted in parallel to the error generation line TQ. In other words,
A RAM test is performed on the recording element that is the subject of the RAM test in units of a predetermined number of bits, and if at least one bit is defective, the error generation line TQ becomes zero potential, indicating that the recording element is defective. I understand that.

Note that the NMOS transistor M7 connected to the reset line R/L is connected to the reset line R/L in preparation for the next test cycle of the recording element to be tested every predetermined number of bits.
It receives a signal from L to H level, becomes conductive, and resets node H to zero potential.

As described above, in this embodiment, the data obtained by directly writing and then reading data to the bit line 2.3 without using the input/output lines 8.9, that is, the data read from the memory cell 5, is used as the write data and the inspection circuit. By checking whether there is a logical match in step 3,
The quality of recording elements can be inspected.

Furthermore, the data write operation to each memory cell connected to the selected word line W/L is possible during one cycle, and the data read operation recorded in each memory cell is also possible in one cycle. Since it is possible between
RAM test time can be significantly reduced.

The present invention is not limited to the above-described embodiments, but can be implemented in any appropriate manner by making appropriate design changes.

[Effects of the Invention] As explained above, according to the method of writing test data to a recording element according to claim (1) of the present invention, a plurality of bit lines connected to a pair of bit lines through which data consisting of a double code is transmitted M
One MOS transistor is selected from the OS transistors, and a charge serving as the data is directly applied to one bit line through the selected MOS transistor, and the charge is transferred to a capacitor in a memory cell connected to the given bit line. Directly transfers and holds the charge serving as the data,
Since there is no input/output line, a large amount of RAM is required.
It can shorten the time required for testing.

According to the method for writing test data to a recording element according to claim (2), at least one MOS transistor is selected from a plurality of MOS transistors connected to a pair of bit lines through which data consisting of double codes is propagated. , directly apply the charge that becomes the data to only one bit line through the selected MoS transistor, hold the other bit line at zero potential, and apply the potential difference between the pair of bit lines to the bit line. The charge amplified by the connected sense amplifier is transferred and held to the capacitor in the memory cell connected to the charged bit line, and the charge is not passed through the input/output bit line. The time required for RAM testing can be shortened, and the sense amplifier amplifies the bit line potential.
Data writing is reliable.

Furthermore, according to the recording element test circuit of claim (3),
A sense amplifier amplifies the potential of a pair of bit lines through which charges that become data of a double code propagate, and absorbs charges applied to the bit lines either directly or after amplification by the sense amplifier according to a signal from a word line. The data is transferred from the bit line to the memory cell through a MOS transistor that is directly connected to each bit line, and the charge that becomes the data is transferred from the bit line to the memory cell. A plurality of data writing means for writing into a memory cell and data checking means for reading the written data written by the means and checking whether the read data matches the written data are provided in parallel, In addition, since the configuration includes a control circuit that controls the operation of the MOS transistor forming the data writing means and transmits a test signal to the data testing means, the method for writing test data to the recording element described above can be carried out. Helpful.

[Brief explanation of the drawing]

FIG. 1 shows a recording element test circuit according to an embodiment of the present invention. 1... Control circuit 2.3... Bit line 4... Bit line potential setting section 5... Memory cell 6... Sense amplifier 7... Inspection circuit 8.9... Input/output line 10 ...Selection section

Claims (5)

[Claims] (1) One MOS transistor is selected from a plurality of MOS transistors connected to a pair of bit lines through which data consisting of a binary code is propagated, and charges that become the data are transferred to one bit line through the selected MOS transistor. 1. A method for writing test data into a recording element, characterized in that the charge forming the data is directly transferred to and held in a capacitor in a memory cell connected to a charged bit line. (2) At least one MOS transistor is selected from a plurality of MOS transistors connected to a pair of bit lines through which data consisting of a binary code is propagated, and the data is transmitted to only one bit line through the selected MOS transistor. a memory cell connected to the bit line to which the electric charge is applied, the other bit line is held at zero potential, the potential difference between the pair of bit lines is amplified by a sense amplifier connected to the bit line, and the electric charge is applied directly to the bit line. A method for writing test data into a recording element, characterized in that the charge amplified by the sense amplifier is transferred to and held in a capacitor in the recording element. (3) A sense amplifier that amplifies the potential of a pair of bit lines through which charges that become data of a binary code propagate; After amplification, the charge that becomes the data given only to one bit line is transferred from the bit line to the memory cell through a memory cell that absorbs and holds it, and a MOS transistor directly connected to each bit line. A plurality of data writing means for writing data into the memory cells and data checking means for reading the write data written by the means and checking whether the read data matches the write data are provided in parallel. , and a control circuit for controlling the operation of a MOS transistor forming the data writing means and transmitting a test signal to the data testing means. (4) The MOS transistors of the data writing means include a PMOS transistor connected to the power supply and an NMOS transistor connected to the ground.
Claim (3) characterized in that it consists of an S transistor.
The recording element test circuit described. (5) The test signal transmitted from the control circuit consists of a first test signal and a second test signal having mutually different potential levels, and the data test means inputs the potential of one bit line to the gate side and a first NMOS transistor that conducts the first test signal in accordance with the potential of the other bit line; a second NMOS transistor that inputs the potential of the other bit line to its gate side and conducts the second test signal in accordance with the potential; and the first NMOS transistor Or the second NMO
3. The recording element test circuit according to claim 3, further comprising a third NMOS transistor which inputs one of the test signals outputted from the S transistor to the gate side and becomes conductive when the read data does not match the write data. .