JPH0728711A - Semiconductor storage - Google Patents

Abstract

PURPOSE:To shorten the test time even for a storage which contains plural memory ICs by turning off equally the output gates that construct an output circuit of each memory IC and also by fixing a data bus at a prescribed potential. CONSTITUTION:A NOR circuit 23 is placed between a logic circuit 40c constructing an error detecting circuit 41 and a mode switching circuit 50b. Then an output transistor 21 connected to a VCC is turned off by a gate control signal Multi TEST, and at the same time a data bus is pulled up at the side of a checking device 9. Therefore a wired OR is secured for the outputs of the memory IC1-IC6 which are connected in parallel to a common data bus. Then plural memory ICs can be tested at a time. Thus it is possible to check whether a storage has a defective IC or not among its (n) pieces of memory ICs in a 1/n checking time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to the facilitation of a test (shortening the test time) of a memory device constructed by using a semiconductor memory.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram including a data writing / reading mechanism used in a test time shortening technique in a 4M DRAM as an example of a conventional semiconductor memory device. In the figure, 10 is a data input terminal, 20 is a memory cell array, and 20a to 20h are memory sub blocks. Mode switching circuit 50a can switch between normal input and test input to each of memory sub blocks 20a to 20h. ing. 3a and 3b respectively indicate the memory sub-blocks 20a to 20a during normal operation.
20h normal output A to H and inverted output / A
It is a data changeover switch for selecting ~ / H and transmitting it to the data output terminal 30.

Reference numeral 40 denotes an error detection circuit, in which the logic circuit 40a receives the normal outputs A to H of the memory sub blocks 20a to 20h, and the logic circuit 40b receives the inverted outputs / A to of the memory sub blocks 20a to 20h. / H.

Further, 50b and 50c respectively receive a test mode signal (/ TEST), and the changeover switch 3 is operated.
a and the output of the logic circuit 40a and the outputs of the changeover switch 3b and the logic circuit 40b to output the mode switching circuits 21 and 22 are the power supply voltage Vcc and the ground G.
An output transistor connected in series with ND,
The data output terminal 30 is connected between the output transistors 21 and 22.

Next, the operation will be described. Note that only the operation during the test will be described here, and the description of the operation during the normal time will be omitted. With the above-described configuration, the test time can be shortened by reading the data simultaneously for 8 bits. For example, since the test is now in progress, when / TEST is set to "L", the transmission gate 26 forming the mode switching circuit 50a is turned off,
The transmission gate 2 turns on the transmission gate 27 and constitutes the mode switching circuit 50b.
4b is turned off, the transmission gate 25b is turned on, and the transmission gate 24c constituting the mode switching circuit 50c is turned off and 25c is turned on.

When the mode switching is performed as described above, the signal applied to the data input terminal 10 is input to each of the memory sub blocks 20a to 20h.
When "0" is input to the data input terminal 10 here, "0" is input to a predetermined cell of each of the memory sub blocks 20a to 20h.
Will be written and read, but at this time,
When "1" is output even for 1 bit by the exclusive OR, the output of the logic circuit 40a becomes "0" and the output of the logic circuit 40b becomes "1". Since the output enable signal (OE) which is one side input of the AND gates 28 and 29 in the subsequent stage is "H", the output transistor 21 is off, the output transistor 22 is on and the data output terminal 30 is at the GND level (" 0 "). Similarly, when "1" is input to the data input terminal 10 and if "0" exists in the read data, the output of the logic circuit 40a becomes "0", the output of the logic circuit 40b becomes "1", and again the data “0” appears at the output terminal 30.

If there is no error in the read data, "1" is output to the logic circuit 40a to turn on the output transistor 21, and "0" is output to the logic circuit 40b to turn off the output transistor 22. As a result, the data output terminal 30 becomes the VCC level ("1").

As described above, "0" or "1" is simultaneously written in 8 bits by the write operation, and then data is simultaneously read out in 8 bits. At this time, if even one bit is different from the written data, the output becomes "0", and if all the bits are correct, it becomes "1".

[0009]

The conventional semiconductor memory device is configured as described above and is intended to test a plurality of bits at the same time to shorten the test time. The purpose is to reduce the test time of each IC, and therefore the main purpose is to reduce the test time of each IC. Therefore, multiple memory ICs
Considering the inspection of a storage device such as a memory card or a memory board on which the IC is mounted, at present, the inspection device individually accesses the memory ICs on the storage device to inspect each, and the inspection is performed on the storage device. When n memory ICs are mounted, there is a problem that the inspection time thereof is n times as long as the inspection time of one memory IC.

The present invention has been made to solve the above-mentioned problems, and a semiconductor device that can reduce the test time even in a storage device such as a memory card or a memory board having a plurality of memory ICs. The purpose is to obtain a storage device.

[0011]

In a semiconductor memory device according to the present invention, the outputs of a plurality of memory ICs in the memory device are connected in parallel to a common data bus, and each memory I is connected.
One of the output gates of the C output circuit is uniformly turned off, and the data bus is fixed to a predetermined potential.

[0012]

According to the present invention, a plurality of memory ICs on a memory device are connected in parallel to a data bus so that only one of the output gates of each memory IC operates uniformly, and the data bus has a predetermined potential. I fixed it to
The output of each memory IC can be wired or ORed.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Semiconductor memory devices according to embodiments of the present invention will be described below. In FIG. 1, the same reference numerals as those in FIG. 3 indicate the same or corresponding portions, and reference numeral 23 is a NOR gate inserted between the logic circuit 40c and the mode switching circuit 50b which constitute the error detection circuit 41, and one input of the NOR gate is provided. The output of the logic circuit 40c on the side to be the input of the gate 21 is input to the other terminal, and the control signal Multi TEST is input to the other input.
Is entered.

FIG. 2 is a block diagram showing a test state of a semiconductor memory device such as a memory card or a memory board having a plurality of memory ICs having the structure shown in FIG. 1 to 6 are IC memories each having the configuration shown in FIG. 1, 8 is a storage device such as a memory card or a memory board, 11 is a decoding circuit for selecting an IC memory connected to a data bus, and 9 is an inspection device. Reference numeral 7 denotes a connector that connects the inspection device 9 and the storage device 8. In the storage device 8, the output of each memory IC is connected in parallel to a common data bus.

Next, the operation will be described. This embodiment has at least two test modes. That is, one uses the test of the memory IC alone (TEST
1) As in the conventional case, this is a mode in which a write / read test is simultaneously performed on 8 bits per one output terminal. Another test mode (TEST2) is multiple memory ICs
This is a mode for shortening the inspection time by simultaneously accessing a plurality of memory ICs at the time of testing the storage device equipped with the. The state of the test control signal in each test mode is as follows.

At normal time (Normal), / TEST is set to "H",
By setting Multi TEST to "L", read data from the memory sub blocks 20a to 20h is decoded by a part of the address signal, passes through the transmission gates 24b and 24c, and the AND gates 28 and 29.
To the output terminal 30 according to these logical values.
CC or GND level appears.

In the TEST1 mode, / TEST
Is set to “L” and Multi TEST is set to “L”,
The NOR gate 23 and the logic circuit 40c perform the same function as that of the logic circuit 40a of FIG. 3 shown in the conventional example, the single memory IC selected by the decoding circuit 11 is tested, and the plurality of memory sub-blocks are tested. At the same time, data of "0" or "1" is written and read at the same time. At this time, if the read data of at least one block is different from the write data, the AND gate 28 sets "L", AN.
The D gate 29 becomes "H" and the output terminal 30 becomes "L".
Appears.

In the TEST2 mode, / TEST is set to "L".
By setting ", Multi TEST" to "H", it is possible to control the state of the output transistor 21 on the pull-up side and simultaneously test a plurality of memory ICs. Is connected to the inspection device 9 through the connector 7, and address signals, data signals, control signals, power supplies, etc. are exchanged through the connector 7. In the storage device 8, a plurality of memory ICs are provided.
1 to 6 are connected in parallel to an address bus and a data bus. Normally, in the inspection of such a storage device, one memory IC is selected by an address signal from the outside (inspection device) and sequentially tested. In this example,
By setting Multi TEST to "H", the output of the NOR gate 23 becomes "L" regardless of the output state of the logic circuit 40c.

Therefore, the output transistor 2 on the pull up side
The gate input of 1 always becomes "L", and the output transistor 21 is turned off. Therefore, in the TEST2 mode, only the pull-down side output circuit (output transistor 22) operates. That is, as in the TEST1 mode, when data of "0" or "1" is simultaneously written, and at the same time all bits are correctly read, the output of the AND gate 29 is "L". Therefore, the output transistor 22 is turned off and the output terminal 30 is in a floating state. On the other hand, if even one bit of read data has an error, the output of the AND gate 29 becomes "H", and therefore the output transistor 22 is turned on.
The output terminal 30 is connected to GND and becomes "L".

At this time, the output of the decode circuit 11 in the memory device is controlled so that a plurality of memory ICs to be tested are selected at the same time. The outputs of the respective memory ICs 1 to 6 are connected in parallel to a common data bus. Therefore, if the data bus is pulled up during the main test on the inspection device 9 side, the respective memory I
The outputs of C1 to C6 are wired-OR, and the memory under test I
If there is an error in the read data with respect to the write data, even if only 1 bit is selected from among C1 to C6, the output terminal 30 of the IC is G
The data bus pulled up becomes "L" because it is connected to ND. If all the read data with respect to the write data are correct, the output terminals 30 of all the IC memories are in a floating state, so the data bus is pulled up. As it is, that is, it becomes "H".

As described above, according to this embodiment, the NOR circuit 23 is provided between the logic circuit 41c forming the error detection circuit 41 and the mode switching circuit 50b, and the gate of the output transistor 21 on the side connected to VCC is provided. Control signal Multi T
Since the inspection device 9 is configured to be turned off by using the EST and the data bus is pulled up on the inspection device 9 side, each memory IC 1 connected in parallel to the common data bus
It is possible to take a wired-OR of the outputs of ~ 6, to test a plurality of memory ICs at the same time, and to determine whether or not a defective IC exists in a memory device having n memory ICs. It can be detected in 1 / n time.

In the above embodiment, the gate of the output transistor 21 on the power supply potential Vcc side is turned off to pull up the data bus. However, conversely, the output transistor 22 on the ground potential GND side of the output transistor 22 is turned off. The gate is turned off, the data bus is pulled down, and the logic is configured so that the logic circuit 40c outputs a signal that turns on the gate of the output transistor 21 when an error is detected during the test. Good.

Further, in FIG. 1, the data input terminal (D
Although the in) and the output terminal (Dout) are provided separately, the same effect can be obtained even if they are provided as the input / output terminals (DI / 0).

[0024]

As described above, according to the semiconductor memory device of the present invention, a plurality of memory ICs on the memory device are connected in parallel to the data bus, and only one of the output gates of each memory IC is uniformly used. Is operated and the data bus is fixed to a predetermined potential, each memory IC
It is possible to take a wired-OR of the outputs of the above, and it is possible to simultaneously test a plurality of memory ICs on the storage device, which has the effect of shortening the inspection time.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram centering on a memory IC of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration for simultaneously testing a plurality of memory ICs in the semiconductor memory device.

FIG. 3 is a diagram showing a configuration of a conventional semiconductor memory device.

[Explanation of symbols]

 1 to 6 memory IC 7 connector 8 storage device 9 inspection device 10 input terminal 11 decoding circuit 20 memory cell array 20a to 20h memory cell block 30 output terminal 40, 41 error detection circuit 40a, 40b logic circuit 50a, 50b, 50c mode switching circuit 21,22 Output transistor 23 NOR gate 24-27 Transmission gate 28,29 gate

Claims (3)

[Claims] 1. A semiconductor memory device having a function of writing the same data to a predetermined address in a memory at the same time for a plurality of bits and then reading the same data to determine whether the data is correct or not. Mode switching means for switching between the read mode and the read mode, a data output terminal connected between the first power source and the second power source, and an output gate connected between the output terminal and each of the power sources. An error detection circuit that controls the output gate in accordance with the result of reading the data and sets the output terminal to a predetermined potential, and an output connection unit that connects a plurality of the output terminals to a common data bus in parallel. And gate-off means for turning off one output gate of the detection circuit based on a control signal, and the data bus is connected to a third power supply. Semiconductor memory device. 2. The semiconductor memory device according to claim 1, wherein the first power supply has a higher potential than the second power supply, and the gate-off means outputs between the first power supply and the output terminal. A semiconductor memory device for turning off a gate, wherein the third power source has a higher potential than the second power source. 3. The semiconductor memory device according to claim 1, wherein the first power supply has a higher potential than the second power supply, and the gate-off means outputs between the second power supply and an output terminal. A semiconductor memory device, wherein a gate is turned off, and the third power supply has a lower potential than the first power supply.