CN1048463A - When testing memory device, write the method for data and the circuit of testing memory device - Google Patents
When testing memory device, write the method for data and the circuit of testing memory device Download PDFInfo
- Publication number
- CN1048463A CN1048463A CN90104915A CN90104915A CN1048463A CN 1048463 A CN1048463 A CN 1048463A CN 90104915 A CN90104915 A CN 90104915A CN 90104915 A CN90104915 A CN 90104915A CN 1048463 A CN1048463 A CN 1048463A
- Authority
- CN
- China
- Prior art keywords
- bit line
- data
- line
- circuit
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 20
- 238000012546 transfer Methods 0.000 claims abstract description 4
- 238000012795 verification Methods 0.000 abstract description 4
- 238000001514 detection method Methods 0.000 abstract 1
- 239000003990 capacitor Substances 0.000 description 8
- 238000012937 correction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000000428 dust Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/30—Accessing single arrays
- G11C29/34—Accessing multiple bits simultaneously
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/36—Data generation devices, e.g. data inverters
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Dram (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The circuit of testing memory device has data transfer apparatus, data detection device and control circuit.The method that writes data during testing memory device comprises the following steps: to produce a voltage difference between a pair of bit line B/L and B/L, and in the electric capacity of memory cell direct stored data.The data of can on bit line, writing direct according to the present invention.In addition, each memory cell of verification and reduced the test duration widely intactly in one-period.
Description
The present invention relates to memory device, DRAM for example, the method for particularly a kind of memory test duration of the memory device that can reduce high density, high integration and the circuit of testing memory device.
The technology that needs various precisions by the integrated memory device of semiconductor fabrication process along with the increase of memory device integration density.Therefore, when carrying out this technology, must avoid dust and impurity.But along with the increase of memory device density, failure rate has also increased.Therefore, memory device has the internal RAM test circuit so that in inside RAM is tested.Even the test of RAM is carried out in inside, along with the increase of integrated level, the test duration also becomes longer.
In other words, in the ram test of routine, ram test is finished with each bit cell of test signal test (X4, X8, X16).The time of test cost with integrated level/* bit increases.Therefore, integrated level is big more, and the test duration is just long more, because writing and reading of data writes or read that each X bit cell is finished and data are mutually relatively so that detect error by input/output line.
An object of the present invention is to provide the wiring method that is used for DRAM, this method by directly writing and comparing data on a pair of bit line, just can detect the correct or wrong of data and reduce the test duration without I/O (I/O) line when data are written into and read.
Another object of the present invention provides the ram test circuit of implementing according to this method.
Write the method for data when in order to achieve the above object, the invention provides the test storage apparatus.This method step is as follows: control circuit gating-MOS transistor, produce a voltage difference between a pair of bit line in case without the I/O line in these data of writing direct on to bit line, in electric capacity, directly store these data by the storage unit of word line gating.
The present invention writes the method for data when the test storage apparatus also is provided.This method step is as follows: at least one MOS transistor of control circuit gating, sensor amplifier drive a pair of bit line with power level (Vcc-level) or ground level (GND-level) and between this is to bit line direct generation one voltage difference, stored data in by the electric capacity of the memory cell of word line gating.
The present invention also provides test to comprise many sensor amplifiers that are connected to a pair of bit line, many memory cells that are connected to bit line and word line, opened by the column selection messenger so that the I/O line is linked the circuit of memory device of many MOS transistor of every pair of bit line respectively according to above-mentioned many memory cells, this circuit comprises the data transfer apparatus that writes data when making this be Vcc-level (power level) and GND-level (ground level) to bit line with the MOS transistor that is directly connected to a pair of bit line, the rear portion that is connected to sensor amplifier is used for the data calibration device of checking data and the control circuit of control data writing station and calibration equipment.
According to the present invention, can on bit line, write direct.In addition, because data are written into each memory cell that is connected to word selection line and carry out error checking on every bit lines, each memory cell of verification and reduce the test duration widely intactly in one-period.
Fig. 1 represents the circuit of the embodiment of the invention.
Now describe the present invention with reference to the accompanying drawings in detail.As shown in Figure 1, in order to detect the differential voltage of bit line, sensor amplifier 2 is between a pair of bit line B/L and B/L.Memory cell 5 is connected between bit line B/L and the word line W/L.Memory cell 5 has a nmos pass transistor M
11With a capacitor C
1In order to keep Vcc-level and ground (GND) level, PMOS transistor M
1With nmos pass transistor M
2Also link bit line B/L respectively.
Similarly, keep the PMOS transistor M of Vcc-level
3With the nmos pass transistor M that keeps the GND-level
4Be connected to bit line B/L.Transistor M
1-M
4Grid be connected to control circuit 1 by node A-D respectively.In addition, nmos pass transistor M
5And M
6Grid link a pair of bit line B/L and B/L respectively and be positioned at the rear portion of sensor amplifier 2.Transistor M
5And M
6Drain electrode also link control circuit 1 by node E and F respectively.
In order to form a checking circuit, be connected to the nmos pass transistor M of reset line
7Linked nmos pass transistor M
5And M
6Common node H and by nmos pass transistor M
8Connect error and produce line TQ.At the rear portion of this checking circuit, by the nmos pass transistor M of column signal COL unlatching
9And M
10Be connected to the I/O line, bit line and I/O line are interconnected.DIN determines now that the status signal of each node A-F is the input data of control circuit 1 when data are written into and read.
Routine operation of the present invention uses the same operation of conventional DRAM, at this moment, and MOS transistor M
1-M
4End.
In the operation of conventional DRAM, MOS transistor M
9And M
10Opened so that select the I/O line by column selection messenger COL, the I/O line is connected to bit line to B/L and B/L and be connected to sensor amplifier 2 then.Sensor amplifier 2 is by bit line and MOS transistor M
11Give the capacitor C of the DRAM unit of selecting by word line W/L and row select lines COL
1Charging.Secondly, for read operation, MOS transistor 11 is opened by word line W/L, is stored in capacitor C
1In electric charge discharge to bit line B/L.For status signal being provided for the I/O line, sensor amplifier 2 detects and amplifies the status signal of bit line.Aforesaid operations is identical with the DRAM operation.But the present invention makes quick ram test without the I/O line, therefore connects the transistor M of I/O line
9And M
10End.
Ram test writes data RAM exactly and compare two data sets after reading recorded data once more.Ram test of the present invention can be divided into two kinds of methods, promptly a kind ofly uses sensor amplifier 2 and another kind does not use sensor amplifier 2 during read operation.
The method of not using sensor amplifier 2 is at first described.This method is during write operation, for the capacitor C in the DRAM unit
1Middle stored data directly provides this data to bit line B/L.Required word line W/L by gating after, control circuit 1 is kept output node A near low level, so PMOS transistor M
1Conducting, B/L provides power source voltage Vcc to bit line.When power source voltage Vcc offers bit line B/L, by the MOS transistor M of word line W/L gating
11Capacitor C is given in conducting
1Charging.Though shown in Figure 1 only is a MOS transistor and a capacitor C
1But, a plurality of MOS transistor of memory and electric capacity can with word line mutually and connect.Supply voltage corresponding to these data also is used to the DRAM unit charging by word line W/L gating.At this constantly, because the data Be Controlled circuit on bit line B/L 1 locks and is imported into node E and F during the read operation of test fast, so sensor amplifier 2 is not worked in this wiring method.
The method of using sensor amplifier 2 is described again.
When control circuit 1 offers node D and A to high level and low level status signal so that make MOS transistor M respectively
1And M
4During conducting, MOS transistor M
1And M
4Conducting and between bit line is to B/L and B/L, produced voltage difference.Read put amplifier 2 detect and amplify this differential voltage and by bit line B/L near Vcc level or GND level charged data into capacitor C thereafter,
1
On the other hand, relatively the compare operation of two data sets is as follows after reading the data that are stored in the DRAM unit to utilize above-mentioned two kinds of wiring methods:
At first, control circuit 1 the status signal of high level offer node A and C, low level status signal gives Node B and D so that make MOS transistor M
1, M
2, M
3And M
4End.Secondly, be that " 1 " and word line W/L make MOS transistor M if be stored in the data of DRAM unit
11Conducting is stored in capacitor C
1Electric capacity discharge to bit line B/L.Sensor amplifier 2 detects these voltages, and bit line B/L is a high level and B/L is a low level.All keep low level reaching above-mentioned level front nodal point E and F.Then, control circuit 1 offers node E and F to the status signal of low level and high level respectively, so just in checking circuit 3 data has been carried out verification (when data are " 1 ").In other words, the low level signal of bit line B/L is added to MOS transistor M
5Grid and the high level signal of bit line B/L is added to MOS transistor M
6Grid, so MOS transistor M
5End and MOS transistor M
6Conducting makes low level state be sent to node H, MOS transistor M
8Continuation ends.
Therefore, the error line TQ that is pre-charged to high level during the read operation of test fast keeps high level state, points out that tested memory cell is normal.If there is error to exist when reading the data that are stored in the memory cell, the signal of high level is sent to node H so that make MOS transistor M
8Conducting, error generation line TQ becomes low level thus, points out to exist error.Therefore, when one of several memory cells fault or each unit had taken place fault has taken place, common node H became high level as mentioned above, points out to have in the DRAM of test error to exist.
Be connected to the MOS transistor M of reset terminal
7Node H is reset to ground level so that carry out next test operation.In other words, write with read operation during, control circuit 1 pre-determines the data (1 or 0) that are stored in memory cell for the output of node A-D and to the node E of checking circuit 3 with checking signal is provided F so that the normal or fault of verification DRAM.
As mentioned above, the present invention by without the I/O line write direct on the bit line or sense data checking data in checking circuit 3 whether correct.The write operation of the data in one-period in being connected to each memory cell of selected word line is possible, and the read operation and the error checking operation that are stored in the data of each memory cell in one-period also are possible, thereby have reduced the test duration of DRAM.
The present invention never only limits to above-described embodiment.With reference to explanation of the present invention, various corrections and other embodiments of the invention of the embodiment that has disclosed will be readily apparent to persons skilled in the art.Therefore appended claim will be used for covering any this correction or the embodiment in the scope of the invention.
Claims (5)
1, the method that writes data during testing memory device comprises the following steps:
Control circuit by gating-MOS transistor produce a voltage difference between a pair of bit line in case without the I/O line this write direct on to bit line data and
Direct stored data in by the electric capacity of the memory cell of word line gating.
2, the method that writes data during testing memory device comprises the following steps:
Control circuit drives a pair of bit line by at least one MOS transistor of gating, sensor amplifier with power level or ground level and directly produce a voltage difference between this is to bit line, and
Stored data in by the electric capacity of the memory cell of word line gating.
3, test comprises many sensor amplifiers that are connected to a pair of bit line, many memory cells that is connected to bit line and word line, is opened by the column selection messenger so that the I/O line is connected respectively to the circuit of memory device of many MOS transistor of every pair of bit line according to above-mentioned many memory cells, and this circuit comprises
Write the data transfer apparatus of data when making this be power level or ground level to bit line with the MOS transistor that is directly connected to a pair of bit line;
The rear portion that is connected to sensor amplifier is used for the data calibration device of checking data; And
The control circuit of control data writing station and calibration equipment.
4, according to the circuit of claim 3, wherein data transfer apparatus comprise directly to this to bit line provide power level the PMOS transistor, provide the nmos pass transistor of ground level to this to bit line, said control circuit is controlled said PMOS and nmos pass transistor.
5, according to the circuit of claim 3, wherein data calibration device comprises that its grid is connected respectively to this nmos pass transistor to bit line, the nmos pass transistor that said control circuit provides locking output and one to be connected between the said nmos pass transistor and driven by verify error to this nmos pass transistor.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR8002/89 | 1989-06-10 | ||
| KR1019890008002A KR920001080B1 (en) | 1989-06-10 | 1989-06-10 | Method writing data and test circuit in memory material |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1048463A true CN1048463A (en) | 1991-01-09 |
| CN1019243B CN1019243B (en) | 1992-11-25 |
Family
ID=19286971
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN90104915A Expired CN1019243B (en) | 1989-06-10 | 1990-06-09 | Method for writing data in testing memory device and circuit for testing memory device |
Country Status (10)
| Country | Link |
|---|---|
| JP (1) | JP3101953B2 (en) |
| KR (1) | KR920001080B1 (en) |
| CN (1) | CN1019243B (en) |
| DE (1) | DE4003132A1 (en) |
| FR (1) | FR2648266B1 (en) |
| GB (1) | GB2232496B (en) |
| IT (1) | IT1248750B (en) |
| NL (1) | NL194812C (en) |
| RU (1) | RU2084972C1 (en) |
| SE (1) | SE512452C2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05128899A (en) * | 1991-10-29 | 1993-05-25 | Mitsubishi Electric Corp | Semiconductor memory |
| AU2003207364A1 (en) * | 2002-02-26 | 2003-09-09 | Koninklijke Philips Electronics N.V. | Non-volatile memory test structure and method |
| CN107430881B (en) * | 2015-03-09 | 2021-03-23 | 东芝存储器株式会社 | Semiconductor memory device with a plurality of memory cells |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59185097A (en) * | 1983-04-04 | 1984-10-20 | Oki Electric Ind Co Ltd | Memory device with self-diagnostic function |
| JPS62229599A (en) * | 1986-03-31 | 1987-10-08 | Toshiba Corp | Nonvolatile semiconductor memory device |
| EP0253161B1 (en) * | 1986-06-25 | 1991-10-16 | Nec Corporation | Testing circuit for random access memory device |
| KR910001534B1 (en) * | 1986-09-08 | 1991-03-15 | 가부시키가이샤 도시바 | Semiconductor memory device |
| JPS6446300A (en) * | 1987-08-17 | 1989-02-20 | Nippon Telegraph & Telephone | Semiconductor memory |
| JPH01113999A (en) * | 1987-10-28 | 1989-05-02 | Toshiba Corp | Stress test circuit for non-volatile memory |
-
1989
- 1989-06-10 KR KR1019890008002A patent/KR920001080B1/en not_active IP Right Cessation
-
1990
- 1990-02-01 FR FR9001203A patent/FR2648266B1/en not_active Expired - Lifetime
- 1990-02-02 JP JP02022322A patent/JP3101953B2/en not_active Expired - Fee Related
- 1990-02-02 DE DE4003132A patent/DE4003132A1/en active Granted
- 1990-02-02 NL NL9000261A patent/NL194812C/en not_active IP Right Cessation
- 1990-02-02 GB GB9002396A patent/GB2232496B/en not_active Expired - Lifetime
- 1990-06-06 SE SE9002030A patent/SE512452C2/en unknown
- 1990-06-07 IT IT02056690A patent/IT1248750B/en active IP Right Grant
- 1990-06-08 RU SU904830256A patent/RU2084972C1/en not_active IP Right Cessation
- 1990-06-09 CN CN90104915A patent/CN1019243B/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JP3101953B2 (en) | 2000-10-23 |
| GB2232496A (en) | 1990-12-12 |
| GB2232496B (en) | 1993-06-02 |
| SE512452C2 (en) | 2000-03-20 |
| KR910001779A (en) | 1991-01-31 |
| GB9002396D0 (en) | 1990-04-04 |
| FR2648266A1 (en) | 1990-12-14 |
| IT9020566A0 (en) | 1990-06-07 |
| DE4003132C2 (en) | 1992-06-04 |
| DE4003132A1 (en) | 1990-12-20 |
| CN1019243B (en) | 1992-11-25 |
| FR2648266B1 (en) | 1993-12-24 |
| NL194812B (en) | 2002-11-01 |
| SE9002030D0 (en) | 1990-06-06 |
| IT1248750B (en) | 1995-01-27 |
| SE9002030L (en) | 1990-12-11 |
| KR920001080B1 (en) | 1992-02-01 |
| IT9020566A1 (en) | 1991-12-07 |
| JPH0312100A (en) | 1991-01-21 |
| NL9000261A (en) | 1991-01-02 |
| RU2084972C1 (en) | 1997-07-20 |
| NL194812C (en) | 2003-03-04 |
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| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C13 | Decision | ||
| GR02 | Examined patent application | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C15 | Extension of patent right duration from 15 to 20 years for appl. with date before 31.12.1992 and still valid on 11.12.2001 (patent law change 1993) | ||
| OR01 | Other related matters |