CN212230079U - Ferroelectric memory storage array structure and ferroelectric memory - Google Patents
Ferroelectric memory storage array structure and ferroelectric memory Download PDFInfo
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Abstract
The utility model provides a ferroelectric memory storage array structure and ferroelectric memory, ferroelectric memory storage array structure includes a plurality of sectors, a plurality of sensing coupled line, selection circuit and a plurality of sensing circuit, wherein: the selection circuit comprises a plurality of selection sub-circuit modules; each sector is respectively connected with the plurality of sensing coupling lines through one selection sub-circuit module; the selection signal controls one selection sub-circuit module in the selection circuit to be switched on and simultaneously controls other selection sub-circuit modules to be switched off so as to isolate other sectors from being coupled to the plurality of sensing coupling lines; the sensing circuits are used for detecting the voltages on the sensing coupling lines so as to judge the storage data of the sector connected with the sensing coupling lines.
Description
Technical Field
The utility model relates to a ferroelectric memory technical field, in particular to ferroelectric memory storage array structure and ferroelectric memory.
Background
A ferroelectric memory, FeRAM, is a new type of memory device fabricated using the hysteresis characteristics of ferroelectric capacitors. The traditional FeRAM memory unit comprises different structures of 2T/2C, 1T/1C and the like.
As shown in fig. 1, it shows a schematic structural diagram of a memory cell of a conventional ferroelectric memory with 1T/1C structure. When reading data stored in a ferroelectric memory cell, the data stored in the cell is judged by comparing the voltage of the BL reading the cell with a reference voltage. As shown in FIG. 1, when reading the stored data of a cell such as bl0 and wl0, the voltage of wl0 is set to 3V, the source-drain path of the transmission transistor connected to wl0 is turned on, the voltage at the point bl0 in the graph is measured, and then the voltage is compared with the reference voltage to judge the data stored in the cell. When calculating the voltage at bl0, the equivalent circuit is as shown in fig. 2, a capacitance Ccell exists between the storage nodes SN (corresponding to bl0 in fig. 1) and PL, the capacitance of the bit line bl <0> is Cm, the bit line bl <0> is not only connected to the word line wl0 through the transfer transistor, but also connected to the word lines wl1 and wl2 … wln-1 through the transfer transistor, and when the potentials of wl1 and wl2 … wln-1 are 0, parasitic capacitances Cgs10, Cgs20 and … Cgsi,0 exist between the bit line bl <0> and the word lines wl1 and wl2 … wln-1, and these capacitances are equivalent to Σ Cgs in fig. 2 because these capacitances are in parallel.
The capacitance of bit line bl0 is Cbl + Σ Cgs _ i, i is 0, …, n-1, where n is the number of rows of word lines;
since Σ Cgs _ i is much larger than Cm, Cbl is approximately equal to Σ Cgs _ i, the voltage of the bit line depends on the number of word lines to which the bit line bl <0> is connected, and the larger the number of connected word lines, the larger the equivalent capacitance Cbl of the bit line.
In calculating the voltage at point bl0, Vbl ═ Vpl × Ccell/(Ccell + Cbl), where Vbl is the sense voltage, i.e., the voltage at storage node SN, and Vpl is the supply voltage, e.g., 3V. As Cbl increases, the value of Vbl decreases, as shown in FIG. 3.
When the stored data is 1, Vbl '1' ═ Vpl × Ccell '1'/(Ccell '1' + Cbl);
when the stored data is 0, Vbl '0' ═ Vpl × Ccell '0'/(Ccell '0' + Cbl); then
Vbl’1’-Vbl’0’＝Vpl×[Ccell’1’/(Ccell’1’+Cbl)-Ccell’0’/(Ccell’0’+Cbl)]；
When Cbl2When the difference between the two is Ccell '1' × Ccell '0', as shown in fig. 4, the difference is the largest.
In summary, the sense voltage is a function of Cbl, and FIG. 3 shows that Vb1, which is the input to the sense amplifier, decreases monotonically with Cbl. This indicates that the input dc bias level is too low for Cbl greater than 100 fF. Fig. 4 shows the relationship of the potential difference between two inputs to Cbl. As Cbl is greater than 100fF, the difference again gradually decreases. As can be seen from fig. 3 and 4, for correct DC bias and sufficiently large differential inputs, the Cbl value should be set around 100 fF. In addition, as can be seen from fig. 2, Cbl is mainly determined by Cgs (gate/source capacitance) of the pass transistors connected to all unselected word lines of bl. The metal capacitance is negligible compared to Σ Cgs. Thus Cbl ∑ Cgs is proportional to the number of wl connected to bl.
Simulation results as shown in FIGS. 3-4 indicate that, in practice, the sense voltage begins to fail when the number of word lines increases to 384 and beyond this range. Since each bit line has a set of sensing circuits, which should be compressed into a narrow space for greater storage density, the peripheral circuits are prevented from occupying a larger space in the bit line direction. If the number of wl in the array is limited, either a set of sense circuits is provided per the limited number of wl bitlines, but then the peripheral circuits are scaled larger relative to the real memory footprint, which will make the chip size incompatible with high density products. The utility model provides a solution can carry the restriction of word line quantity in order to eliminate every sensing circuit.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a ferroelectric memory storage array structure and ferroelectric memory to because the word line quantity restriction that the bit line is connected among the current ferroelectric memory of solution, and need set up multiunit sensing circuit and lead to the great problem of memory area.
In order to solve the above technical problem, the utility model provides a ferroelectric memory storage array structure, ferroelectric memory storage array structure includes a plurality of sectors, a plurality of sensing coupling line, selection circuit and a plurality of sensing circuit, wherein:
the selection circuit comprises a plurality of selection sub-circuit modules;
each sector is respectively connected with the plurality of sensing coupling lines through one selection sub-circuit module;
one selection sub-circuit module in the selection circuit array is switched on, and other selection sub-circuit modules are switched off;
the sensing circuits are used for detecting voltages on the sensing coupling lines so as to read storage data of a sector connected with the sensing coupling lines.
Optionally, in the ferroelectric memory storage array structure, the sector includes a plurality of sub-storage units arranged in rows and columns, wherein:
in each sector, a plurality of sub memory cells are arranged in a matrix structure of i rows and j columns;
the plurality of sub-memory units are all connected with the plate line, the sub-memory units in the same row are all connected with the word line corresponding to the row, and the sub-memory units in the same column are all connected with the bit line corresponding to the column.
Optionally, in the ferroelectric memory array structure, the sub memory cell includes a ferroelectric capacitor and a pass transistor, the ferroelectric capacitor has a first plate and a second plate, and the first plate is connected to the plate line;
the transmission transistor is provided with a source-drain path and a grid electrode, the source-drain path of the transmission transistor is connected between the second polar plate and the bit line corresponding to the row, and the grid electrode of the transmission transistor is coupled to the word line corresponding to the row.
Optionally, in the ferroelectric memory storage array structure, the ferroelectric memory storage array structure further includes a reference voltage generating circuit, where:
the reference voltage generating circuit comprises a plurality of reference sub-memory units, the reference sub-memory units are arranged in a matrix structure with multiple rows and 2 columns, and each row of the reference sub-memory units shares the same word line with one row of sub-memory units of the fan-out memory structure;
the reference sub-storage units are connected with the plate line, the reference sub-storage units in a first row output a first reference voltage, and the reference sub-storage units in a second row output a second reference voltage;
the voltage of the plate line connected with the selected sub-memory cell is a power supply voltage;
the voltage of the word line connected with the selected sub-memory cell is a power supply voltage, and the second plate of the ferroelectric capacitor is conducted with the bit line;
the voltage on the bit line is a sensing voltage, and one half of the difference between the first reference voltage and the second reference voltage is a reference voltage;
the sensing voltage and the reference voltage are both coupled to the plurality of sensing circuits.
Optionally, in the memory array structure of the ferroelectric memory, the ferroelectric capacitor includes a first capacitor and a second capacitor, the pass transistor includes a first transistor and a second transistor, and the bit line includes a true bit line and a complementary bit line, where:
the source-drain path of the first transistor is connected between the second polar plate of the first capacitor and the true bit line corresponding to the column, and the source-drain path of the second transistor is connected between the second polar plate of the second capacitor and the complementary bit line corresponding to the column;
the voltage of the plate line connected with the selected sub-memory cell is a power supply voltage;
the voltage of the word line connected with the selected sub-memory cell is a power supply voltage, conduction is carried out between the second plate of the first capacitor and the true bit line, and conduction is carried out between the second plate of the second capacitor and the complementary bit line;
the voltage on the true bit line is a sensing voltage, and the voltage on the complementary bit line is a reference voltage;
the sensing voltage and the reference voltage are both coupled to the plurality of sensing circuits.
Optionally, in the ferroelectric memory storage array structure, a plurality of the sectors are arranged in rows, and a plurality of the sectors are arranged in a matrix structure of k rows;
the selection sub-circuit modules are arranged in rows, the number of the rows of the selection sub-circuit modules is k, the selection sub-circuit modules correspond to the sectors one by one, and each selection sub-circuit module comprises a j column selection switch;
and j columns of sub-memory cells of each sector are respectively connected with j column selection switches of the selection sub-circuit module corresponding to the sector one by one.
Optionally, in the ferroelectric memory storage array structure, the sensing coupled lines include j columns of sensing coupled lines, and the sensing circuit includes j sense amplifiers;
j columns of sensing coupling lines correspond to j columns of sub memory cells in each sector, and j columns of sensing coupling lines correspond to j sensing amplifiers;
each column of sensing coupling lines is connected between the corresponding sub-memory unit and the sensing amplifier;
in each sector, the bit line of the mth column is connected with the mth sense amplifier through the sense coupling line of the mth column;
in k sectors, a total of k bit lines are connected to a sense amplifier through a sense coupling line.
Optionally, in the ferroelectric memory storage array structure, the ferroelectric memory storage array structure further includes a command decoder and an address decoder, wherein:
the command decoder is configured to encode according to a memory control instruction, form a memory address, and send the memory address to the address decoder, and the address decoder is configured to decode the memory address, generate a selection signal, and send the selection signal to a selection circuit.
Optionally, in the ferroelectric memory storage array structure, the selection switch includes a first switch transistor, a second switch transistor, and an inverter, wherein:
an input of the inverter is coupled to the address decoder;
the first switch transistor is provided with a source-drain path and a grid electrode, the source-drain path of the first switch transistor is connected between the bit line and the sensing coupling line, and the grid electrode of the first switch transistor is coupled to the address decoder;
the second switch transistor is provided with a source-drain path and a grid electrode, the source-drain path of the second switch transistor is connected between the bit line and the sensing coupling line, and the grid electrode of the second switch transistor is coupled to the output end of the phase inverter.
The utility model also provides a ferroelectric memory, it includes:
a plurality of memory sectors, each of which is a sector of memory,
each memory sector comprises a plurality of memory cell arrays, each memory cell array comprises k rows and j columns of memory cells, and each memory cell comprises a word line, a bit line and a plate line;
a plurality of sensing circuits, each sensing circuit connected to a bit line of a column of memory cells of each sector;
and the selection switches are respectively connected with the bit lines of each column of memory cells of each sector and the corresponding sensing circuit, and can be switched on or off under the control of a control signal, and only one sector is switched on at a time.
In the ferroelectric memory array structure and the ferroelectric memory provided by the utility model, each sector is respectively connected with a plurality of sensing coupling lines through a selection sub-circuit module, the selection signal controls the conduction of one selection sub-circuit module in the selection circuit and simultaneously controls the turn-off of other selection sub-circuit modules, so as to isolate other sectors from being coupled to a plurality of sensing coupling lines, and realize that only one sector is connected with the sensing circuit when reading, thus when reading a certain unit, the equivalent capacitance of the bit line to which the sensing circuit is connected need only take into account the word line parasitic capacitance of the sector to which the bit line is connected, therefore, the number of word lines connected with the bit line during reading can be reduced, and the phenomenon that if a plurality of sectors are connected at the same time and the number of unselected cells is large, the sensing precision is greatly reduced by superposed interference until the unselected cells fail is avoided.
In the existing memory, because the number of bit lines connected to the word lines is limited, a group of sensing circuits is usually configured for 16kbit memory cells, because the 16kbit memory cells are equal to an array of 256 rows of word lines × 64 columns of bit lines, so that the number of word lines connected to each bit line is 256 without the limit of more than 384. Because a 16-kbit storage unit occupies a unit storage space, and a corresponding sensing circuit also occupies a unit storage space, such a 16-kbit storage unit plus a sensing circuit occupies 2 unit storage spaces, the total of 64 16-kbit storage units of the 1M memory occupies 128 unit storage spaces. And the utility model discloses an every sector includes 16kbit memory cell, a set of sensing circuit of 32 sector sharing, and the shared space of 1M's memory is (32 sector +1 group sensing circuit) × 2 ═ 66 unit storage spaces like this, is 1M's capacity equally, greatly reduced the space that the memory occupy, increased the storage density of ferroelectric memory storage array structure.
Drawings
FIG. 1 is a schematic diagram of a conventional ferroelectric memory array structure;
FIG. 2 is a schematic diagram of an equivalent circuit of a sub-memory cell in a conventional ferroelectric memory array structure during data reading;
FIG. 3 is a diagram illustrating the data reading simulation result of sub-memory cells in a conventional ferroelectric memory array structure;
FIG. 4 is a diagram illustrating the data reading simulation result of sub-memory cells in a conventional ferroelectric memory array structure;
fig. 5 is a schematic structural diagram of a single sector 1T1C in a ferroelectric memory array structure according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a single sector 2T2C in a ferroelectric memory array structure according to another embodiment of the present invention;
fig. 7 is an overall schematic diagram of a ferroelectric memory array structure according to another embodiment of the present invention;
fig. 8 is a schematic diagram of a method for selecting sectors for a ferroelectric memory storage array structure according to another embodiment of the present invention;
fig. 9 is a schematic diagram of a select switch control system in a ferroelectric memory array structure according to another embodiment of the present invention;
fig. 10 is a schematic structural diagram of a select switch in a ferroelectric memory storage array structure according to another embodiment of the present invention;
shown in the figure: 10-a command decoder; 20-address decoder.
Detailed Description
The ferroelectric memory array structure and the ferroelectric memory proposed by the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more fully apparent from the following description and appended claims. It should be noted that the drawings are in simplified form and are not to precise scale, and are provided for convenience and clarity in order to facilitate the description of the embodiments of the present invention.
The core idea of the utility model is to provide a ferroelectric memory storage array structure and ferroelectric memory to solve current ferroelectric memory because the word line quantity restriction that the bit line is connected, and need set up multiunit sensing circuit and lead to the great problem of memory area.
In order to realize the above idea, the utility model provides a ferroelectric memory storage array structure and ferroelectric memory, ferroelectric memory storage array structure includes a plurality of sectors, a plurality of sensing coupling line, selection circuit and a plurality of sensing circuit, wherein: the selection circuit comprises a plurality of selection sub-circuit modules; each sector is respectively connected with the plurality of sensing coupling lines through one selection sub-circuit module; the selection signal controls one selection sub-circuit module in the selection circuit to be switched on and simultaneously controls other selection sub-circuit modules to be switched off so as to isolate other sectors from being coupled to the plurality of sensing coupling lines; the sensing circuits are used for detecting the voltages on the sensing coupling lines so as to judge the storage data of the sector connected with the sensing coupling lines.
The present embodiment provides a ferroelectric memory array structure, as shown in fig. 7, which includes a plurality of sectors (sector0 and sector1 … shown in fig. 7), a plurality of sensing coupled lines (sa _ bl <0> … sa _ bl <62>, sa _ bl <63> shown in fig. 7), a selection circuit, and a plurality of sensing circuits (U0 … U62 and U63 shown in fig. 7), wherein: the selection circuit comprises a plurality of selection sub-circuit modules (for example, the switches K00 … K620 and K630 in fig. 7 form a first selection sub-circuit module select sector0, and the switches K01 … K621 and K631 form a second selection sub-circuit module select sector 1); each of the sectors is connected to the plurality of sense coupling lines through one of the selection sub-circuit blocks (e.g., in sector1, bit line bl01 is connected to sa _ bl <0> through K01 in the second selection sub-circuit block select 1, … bit line bl621 is connected to sa _ bl <62> through K621, and bit line bl631 is connected to sa _ bl <63> through K631); a selection signal (e.g., a signal provided to a second selection sub-circuit block select sector1 shown in fig. 7) controls one of the selection sub-circuit blocks to turn on while controlling the other selection sub-circuit blocks to turn off to isolate the other sectors from being coupled to the plurality of sense coupling lines; the select signal provided to select sector1 controls the connection or disconnection of the bitline of sector1 to the sense coupling line by controlling the turn on and off of second select sub-circuit block select sector1, and the select signal provided to select sector0 controls the connection or disconnection of the bitline of sector0 to the sense coupling line by controlling the turn on and off of first select sub-circuit block select sector 0; when the bit line of sector1 is electrically connected to the sense coupling line, the other sectors including sector0 are electrically disconnected from the sense coupling line; the sensing lines are connected to the sensing circuits, and the sensing circuits are used for detecting voltages on the sensing lines to determine stored data of a sector (i.e., sector1 in fig. 7) connected thereto.
Specifically, as shown in fig. 5 to 6, fig. 5 shows a ferroelectric memory with a 1T/1C structure, and fig. 6 shows a ferroelectric memory with a 2T/2C structure. In the ferroelectric memory storage array structure, the sector includes a plurality of sub-storage units arranged in rows and columns, wherein: in each sector, a plurality of sub memory cells are arranged in a matrix structure of i rows and j columns; the sub-memory cells are all connected to a plate line PL, the sub-memory cells in the same row are all connected to word lines (wl0, wl1, … wli) corresponding to the row, and the sub-memory cells in the same column are all connected to bit lines (bl0, bl1, … blj) corresponding to the column. In the ferroelectric memory storage array structure, the sub-storage units comprise a ferroelectric capacitor Mcell and a transmission transistor Ccell, wherein the ferroelectric capacitor Ccell is provided with a first polar plate and a second polar plate, and the first polar plate is connected with the plate line PL; the transmission transistor Mcell is provided with a source-drain path and a gate, the source-drain path of the transmission transistor Mcell is connected between the second polar plate and a bit line (bl0, bl1, … blj) corresponding to the current column, and the gate of the transmission transistor Mcell is coupled to a word line (wl0, wl1, … wli) corresponding to the current row.
Further, in the ferroelectric memory storage array structure, the ferroelectric memory storage array structure further includes a reference voltage generating circuit, wherein: the reference voltage generating circuit comprises a plurality of reference sub-storage units, the reference sub-storage units are arranged in a matrix structure with a plurality of rows and 2 columns, the first column generates a sensing voltage when data is 1, the second column generates a sensing voltage when the data is 0, and each row of the reference sub-storage units and one row of sub-storage units of the fan-out storage structure share the same word line; the reference sub memory cells are all connected to the plate line PL, the reference sub memory cells of a first column output a first reference voltage (a sense voltage when data is 1, and the capacitance Cref1 has been polarized by writing data 1), the reference sub memory cells of a second column output a second reference voltage (a sense voltage when data is 0, and the capacitance Cref0 has been polarized by writing data 0); when a certain sub-memory cell is selected, the voltage of the plate line is a power supply voltage Vcc; the voltage of the word line connected with the selected sub-memory cell is a power supply voltage, and the second plate of the ferroelectric capacitor is conducted with the bit line; the voltage on the bit line is a sensing voltage, and one half of the difference between the first reference voltage and the second reference voltage is a reference voltage; the sensing voltage and the reference voltage are both coupled to the plurality of sensing circuits.
As shown in fig. 6, in the ferroelectric memory storage array structure, the ferroelectric capacitor Ccell includes a first capacitor Ccell1 and a second capacitor Ccell2, the transfer transistor Mcell includes a first transistor Mcell1 and a second transistor Mcell2, and the bit line (for example, bl0) includes a true bit line bl0a and a complementary bit line bl0b, where: a source-drain path of the first transistor Mcell1 is connected between the second plate of the first capacitor Ccell1 and the true bit line bl0a corresponding to the column, a source-drain path of the second transistor Mcell2 is connected between the second plate of the second capacitor Ccell2 and the complementary bit line bl0b corresponding to the column, polarization directions of the first capacitor Ccell1 and the second capacitor Ccell2 are opposite, that is, if the data stored in the Ccell1 is 1, the data 0 is stored in the Ccell 2; when a certain sub memory cell is selected, the voltage of the plate line PL is a power supply voltage Vcc; the voltage of the word line (for example, wl 1) connected to the selected sub-memory cell is the power supply voltage Vcc, conduction is established between the second plate of the first capacitor Ccell1 and the true bit line bl0a, and conduction is established between the second plate of the second capacitor Ccell2 and the complementary bit line bl0 b; the voltage on the true bit line bl0a is the sensing voltage and the voltage on the complement bit line bl0b is the reference voltage; the sensing voltage and the reference voltage are both coupled to the plurality of sensing circuits.
As shown in fig. 7 to 8, in the ferroelectric memory array structure, a plurality of the sectors are arranged in rows, and a plurality of the sectors are arranged in a matrix structure of k rows (sector0, sector1, … sector-1); a plurality of the selection sub-circuit modules are arranged in rows, the number of rows of the selection sub-circuit modules is k rows (such as sel sec0, sel sec1 and … sel sec-1 shown in FIG. 8), and the selection sub-circuit modules are in one-to-one correspondence with the sectors (sector0, sector1 and … sector-1) (namely, bit lines sec0 bl, sec 1bl and … sector-1 bl connected with the fan-out storage structures shown in FIG. 8); each of the selection sub-circuit blocks includes a j column select switch (in one embodiment provided in fig. 7, each of the selection sub-circuit blocks includes 64 column select switches, e.g., the selection sub-circuit block corresponding to sector1 includes K01, … K621, K631); the j column sub-memory cells of each sector are respectively connected to the j column selection switches of the selection sub-circuit module corresponding to the sector one by one (as shown in fig. 7, bl00, … bl620, bl630 in sector0 are respectively connected to the selection switches K00, … K620, K630 of the selection sub-circuit module corresponding to the sector one by one, and bl01, … bl621, bl631 in sector1 are respectively connected to the selection switches K01, … K621, K631 of the selection sub-circuit module corresponding to the sector one by one). In the ferroelectric memory storage array structure, the plurality of sensing coupled lines includes j columns of sensing coupled lines (64 columns as shown in fig. 7, sa _ bl <0> … sa _ bl <62>, sa _ bl <63>), and the plurality of sensing circuits includes j sensing amplifiers (64 columns as shown in fig. 7, U0 … U62, U63); the j columns of sensing coupled lines sa _ bl <0> … sa _ bl <62>, sa _ bl <63> correspond to the j columns of sub-memory cells in each sector, and the j columns of sensing coupled lines sa _ bl <0> … sa _ bl <62>, sa _ bl <63> correspond to the j sensing amplifiers U0 … U62, U63; each column of sense coupled lines is connected between its corresponding sub-memory cell and the sense amplifier. Those skilled in the art will appreciate that j is equal to 64 columns for the example, and that other numbers of columns may be used in a practical implementation. In each sector, the bit line of the mth column is connected with the mth sense amplifier through the sense coupling line of the mth column; in k sectors, a total of k bit lines are connected to a sense amplifier through a sense coupling line.
As shown in fig. 9, in the ferroelectric memory storage array structure, the ferroelectric memory storage array structure further includes a command decoder 10 and an address decoder 20, in this embodiment of the present invention, 32 sectors share a set of sensing circuits, so when reading a certain storage unit, it is first necessary to determine which sector is selected through the address decoder, wherein: the command decoder 10 encodes according to a storage control instruction to form a storage address (e.g., Sector _ address <4:0>, which is a binary address with a maximum addressing address of 11111, and corresponds to 32 sectors), and sends the storage address Sector _ address <4:0> to the address decoder 20, and the address decoder 20 decodes the storage address to generate a high-level selection signal Select _ Sector <31:0>, which indicates that a 32 th Sector (with an address of 11111) is selected, and sends the selection signal Select _ Sector <31:0> to a selection circuit, that is, a selection sub-circuit module connected to the Sector31 is turned on because of the Select _ Sector <31:0>, and other selection sub-circuit modules are turned off. Wherein the address decoder 20 may include a row decoder and a column decoder by which it is finally determined that a certain memory cell is selected.
As shown in fig. 10, in the ferroelectric memory array structure, the selection switch includes a first switching transistor M1, a second switching transistor M2, and an inverter F1, wherein: the input of the inverter F1 is coupled to the address decoder 20; the first switch transistor M1 has a source-drain path and a gate, the source-drain path of the first switch transistor M1 is connected between the bit line Sector <31> bl < i > and the sensing coupling line sa _ bl < i >, and the gate of the first switch transistor M1 is coupled to the address decoder 20; the second switch transistor M2 has a source-drain path and a gate, the source-drain path of the second switch transistor M2 is connected between the bit line Sector <31> bl < i > and the sensing coupling line sa _ bl < i >, and the gate of the second switch transistor M2 is coupled to the output end of the inverter F1. When the 32 th Sector is selected, the selection signal Select _ selector <31:0> is high, and both the first switching transistor and the second switching transistor are turned on. The second switching transistor M2 is used as a redundant transistor of the first switching transistor M1, and redundant conduction is realized when the first switching transistor is damaged, so that the operation of the memory cell is not influenced.
In summary, the above embodiments have described the details of different configurations of the ferroelectric memory array structure, and of course, the present invention includes but is not limited to the configurations listed in the above embodiments, and any modifications based on the configurations provided by the above embodiments are within the scope of the present invention. One skilled in the art can take the contents of the above embodiments to take a counter-measure.
The present embodiment also provides a ferroelectric memory, including: a plurality of memory sectors, each memory sector including a plurality of memory cell arrays, each memory cell array including k rows and j columns of memory cells, each memory cell including a word line, a bit line, and a plate line; a plurality of sensing circuits, each sensing circuit connected to a bit line of a column of memory cells of each sector; and the selection switches are respectively connected with the bit lines of each column of memory cells of each sector and the corresponding sensing circuit, and can be switched on or off under the control of a control signal, and only one sector is switched on at a time.
In the ferroelectric memory array structure and the ferroelectric memory provided by the utility model, each sector is respectively connected with a plurality of sensing coupling lines through a selection sub-circuit module, the selection signal controls the conduction of one selection sub-circuit module in the selection circuit and simultaneously controls the turn-off of other selection sub-circuit modules, so as to isolate other sectors from being coupled to a plurality of sensing coupling lines, and realize that only one sector is connected with the sensing circuit when reading, thus when reading a certain unit, the equivalent capacitance of the bit line to which the sensing circuit is connected need only take into account the word line parasitic capacitance of the sector to which the bit line is connected, therefore, the number of word lines connected with the bit line during reading can be reduced, and the phenomenon that if a plurality of sectors are connected at the same time and the number of unselected cells is large, the sensing precision is greatly reduced by superposed interference until the unselected cells fail is avoided.
In addition, the ferroelectric memory of the present invention, 32 sectors share a set of sensing circuit, generally, the 16kbit memory cell is equal to the array of 256 rows of word lines × 64 columns of bit lines, the array occupies a unit memory space, and 64 columns of multiple sensing circuits also occupy a unit memory space, if not interfered, only 256 rows of word lines are connected, then the memory cell array and multiple sensing circuits share two unit memory spaces, respectively occupy 50% of the space, another 16kbit memory cell needs two unit memory spaces, 1M memory space is 64 16kbit memory cells, and occupies 128 unit memory spaces. And take the utility model discloses an behind the embodiment, 64 16 kbit's the memory cell occupies 64 unit memory space, in addition, every a plurality of sensing circuit detect for 32 16 kbit's the memory cell, need two a plurality of sensing circuits altogether, occupy two unit memory spaces, need 66 unit memory spaces altogether, greatly increased ferroelectric memory storage array structure's storage density.
The above description is only for the preferred embodiment of the present invention and is not intended to limit the scope of the present invention, and any modification and modification made by those skilled in the art according to the above disclosure are all within the scope of the claims.
Claims (10)
1. A ferroelectric memory array structure, comprising a plurality of sectors, a plurality of sense coupling lines, a selection circuit, and a plurality of sense circuits, wherein:
the selection circuit comprises a plurality of selection sub-circuit modules;
each sector is respectively connected with the plurality of sensing coupling lines through one selection sub-circuit module;
one selection sub-circuit module in the selection circuit array is switched on, and other selection sub-circuit modules are switched off;
the sensing circuits are used for detecting voltages on the sensing coupling lines so as to read storage data of a sector connected with the sensing coupling lines.
2. A ferroelectric memory storage array structure as in claim 1, wherein said sector comprises a plurality of sub-memory cells arranged in rows and columns, wherein:
in each sector, a plurality of sub memory cells are arranged in a matrix structure of i rows and j columns;
the plurality of sub-memory units are all connected with the plate line, the sub-memory units in the same row are all connected with the word line corresponding to the row, and the sub-memory units in the same column are all connected with the bit line corresponding to the column.
3. The ferroelectric memory array structure of claim 2, wherein the sub-memory cells comprise a ferroelectric capacitor and a pass transistor, the ferroelectric capacitor having a first plate and a second plate, the first plate being connected to the plate line;
the transmission transistor is provided with a source-drain path and a grid electrode, the source-drain path of the transmission transistor is connected between the second polar plate and the bit line corresponding to the row, and the grid electrode of the transmission transistor is coupled to the word line corresponding to the row.
4. A ferroelectric memory array structure as in claim 3, further comprising a reference voltage generating circuit, wherein:
the reference voltage generating circuit comprises a plurality of reference sub-memory units, the reference sub-memory units are arranged in a matrix structure with multiple rows and 2 columns, and each row of the reference sub-memory units shares the same word line with one row of sub-memory units of the fan-out memory structure;
the reference sub-storage units are connected with the plate line, the reference sub-storage units in a first row output a first reference voltage, and the reference sub-storage units in a second row output a second reference voltage;
the voltage of the plate line connected with the selected sub-memory cell is a power supply voltage;
the voltage of the word line connected with the selected sub-memory cell is a power supply voltage, and the second plate of the ferroelectric capacitor is conducted with the bit line;
the voltage on the bit line is a sensing voltage, and one half of the difference between the first reference voltage and the second reference voltage is a reference voltage;
the sensing voltage and the reference voltage are both coupled to the plurality of sensing circuits.
5. The ferroelectric memory array structure of claim 3, wherein the ferroelectric capacitor comprises a first capacitor and a second capacitor, the pass transistor comprises a first transistor and a second transistor, the bit line comprises a true bit line and a complementary bit line, wherein:
the source-drain path of the first transistor is connected between the second polar plate of the first capacitor and the true bit line corresponding to the column, and the source-drain path of the second transistor is connected between the second polar plate of the second capacitor and the complementary bit line corresponding to the column;
the voltage of the plate line connected with the selected sub-memory cell is a power supply voltage;
the voltage of the word line connected with the selected sub-memory cell is a power supply voltage, conduction is carried out between the second plate of the first capacitor and the true bit line, and conduction is carried out between the second plate of the second capacitor and the complementary bit line;
the voltage on the true bit line is a sensing voltage, and the voltage on the complementary bit line is a reference voltage;
the sensing voltage and the reference voltage are both coupled to the plurality of sensing circuits.
6. A ferroelectric memory array structure as in claim 2, wherein a plurality of said sectors are arranged in rows, a plurality of said sectors being arranged in a matrix structure of k rows;
the selection sub-circuit modules are arranged in rows, the number of the rows of the selection sub-circuit modules is k, the selection sub-circuit modules correspond to the sectors one by one, and each selection sub-circuit module comprises a j column selection switch;
and j columns of sub-memory cells of each sector are respectively connected with j column selection switches of the selection sub-circuit module corresponding to the sector one by one.
7. The ferroelectric memory array structure of claim 6, wherein the sense coupled lines comprise j columns of sense coupled lines, the sense circuitry comprises j sense amplifiers;
j columns of sensing coupling lines correspond to j columns of sub memory cells in each sector, and j columns of sensing coupling lines correspond to j sensing amplifiers;
each column of sensing coupling lines is connected between the corresponding sub-memory unit and the sensing amplifier;
in each sector, the bit line of the mth column is connected with the mth sense amplifier through the sense coupling line of the mth column;
in k sectors, a total of k bit lines are connected to a sense amplifier through a sense coupling line.
8. A ferroelectric memory array structure as in claim 6, further comprising a command decoder and an address decoder, wherein:
the command decoder is configured to encode according to a memory control instruction, form a memory address, and send the memory address to the address decoder, and the address decoder is configured to decode the memory address, generate a selection signal, and send the selection signal to a selection circuit.
9. The ferroelectric memory storage array structure of claim 8, wherein the selection switch comprises a first switch transistor, a second switch transistor, and an inverter, wherein:
an input of the inverter is coupled to the address decoder;
the first switch transistor is provided with a source-drain path and a grid electrode, the source-drain path of the first switch transistor is connected between the bit line and the sensing coupling line, and the grid electrode of the first switch transistor is coupled to the address decoder;
the second switch transistor is provided with a source-drain path and a grid electrode, the source-drain path of the second switch transistor is connected between the bit line and the sensing coupling line, and the grid electrode of the second switch transistor is coupled to the output end of the phase inverter.
10. A ferroelectric memory, comprising:
a plurality of memory sectors, each of which is a sector of memory,
each memory sector comprises a plurality of memory cell arrays, each memory cell array comprises k rows and j columns of memory cells, and each memory cell comprises a word line, a bit line and a plate line;
a plurality of sensing circuits, each sensing circuit connected to a bit line of a column of memory cells of each sector;
and the selection switches are respectively connected with the bit lines of each column of memory cells of each sector and the corresponding sensing circuit, and can be switched on or off under the control of a control signal, and only one sector is switched on at a time.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112712831A (en) * | 2021-01-13 | 2021-04-27 | 无锡拍字节科技有限公司 | Ferroelectric memory and operation method thereof |
| CN114121084A (en) * | 2021-11-26 | 2022-03-01 | 海光信息技术股份有限公司 | Storage device, detection method and device, and storage medium |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112712831A (en) * | 2021-01-13 | 2021-04-27 | 无锡拍字节科技有限公司 | Ferroelectric memory and operation method thereof |
| CN112712831B (en) * | 2021-01-13 | 2024-01-26 | 无锡舜铭存储科技有限公司 | Ferroelectric memory and operation method thereof |
| CN114121084A (en) * | 2021-11-26 | 2022-03-01 | 海光信息技术股份有限公司 | Storage device, detection method and device, and storage medium |
| CN114121084B (en) * | 2021-11-26 | 2024-03-29 | 海光信息技术股份有限公司 | Storage device, detection method and device, and storage medium |
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