CN112712831B - Ferroelectric memory and operation method thereof - Google Patents
Ferroelectric memory and operation method thereof Download PDFInfo
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- CN112712831B CN112712831B CN202110043971.4A CN202110043971A CN112712831B CN 112712831 B CN112712831 B CN 112712831B CN 202110043971 A CN202110043971 A CN 202110043971A CN 112712831 B CN112712831 B CN 112712831B
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- 238000005859 coupling reaction Methods 0.000 claims description 30
- 230000000087 stabilizing effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 14
- 230000005684 electric field Effects 0.000 description 13
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2273—Reading or sensing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2253—Address circuits or decoders
- G11C11/2255—Bit-line or column circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2275—Writing or programming circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2297—Power supply circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
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Abstract
The invention discloses a ferroelectric memory, which comprises a plurality of byte memory cells and a first selection circuit. Each byte memory cell comprises a plurality of memory cells, each memory cell comprises a bit line and a plate line, and the plate lines of the byte memory cells are independent. The first selection circuit comprises a plurality of first selection sub-circuit modules, one end of each first selection sub-circuit module is electrically connected to the bit line of each storage unit of each byte storage unit, the other end of each first selection sub-circuit module is connected to a plurality of corresponding sensing circuits, the sensing circuits output sensing signals according to input signals of the bit lines of the connected storage units, and when the first selection sub-circuit module corresponding to any byte storage unit is turned on, the first selection sub-circuit modules corresponding to the other byte storage units are turned off.
Description
Technical Field
The present invention relates to the field of ferroelectric memory technology, and in particular, to a ferroelectric memory and a method for operating the same.
Background
In recent years, ferroelectric memories have received increasing attention as a new type of memory with high writing speed and high number of reading and writing. Ferroelectric memory is a special process nonvolatile memory. When an electric field is applied to a ferroelectric transistor, the central atoms stay in a first low energy state along the electric field, and when an electric field reversal is applied to the same ferroelectric transistor, the central atoms move in the crystal along the direction of the electric field and stay in a second low energy state. A large number of central atoms move and couple in the crystal unit cell to form ferroelectric domains, which form polarized charges under the action of an electric field. The ferroelectric domain is inverted under the electric field to form high polarized charge, the ferroelectric domain is not inverted under the electric field to form low polarized charge, and the binary stable state of the ferroelectric material enables the ferroelectric to be used as a memory.
After the electric field is removed, the central atom is kept in a low-energy state, and the state of the memory is kept and cannot disappear, so that the memory cell can be judged to be in a '1' state or a '0' state by high-polarization charge formed by inversion or low-polarization charge formed by non-inversion of the ferroelectric domain under the electric field. The inversion of ferroelectric domains does not require a high electric field, but can change the state of "1" or "0" of the memory cell with only a general operating voltage; nor does a charge pump need to generate a high voltage for data erasure, and thus there is no erasure delay. The characteristics enable the ferroelectric memory to continue to store data after power failure, and the ferroelectric memory has high writing speed, infinite writing life and difficult writing damage. Moreover, ferroelectric memories have higher writing speeds and longer read and write lives than existing nonvolatile memory technologies.
Reading of ferroelectric memory as shown in fig. 1, when reading data stored in a ferroelectric cell, the data stored in the cell is judged by the potential difference between the bit line bl and the reference line of the cell. As shown in the figure, when the stored data of the corresponding cell of bl <0>, wl0 is read, the voltage of wl0 is set at high level, so that the source-drain path of the transmission transistor connected with wl0 is conducted, which is equivalent to the fact that the storage node bl0 is directly connected to the bit line bl <0>, the corresponding reference point blref0 is connected to the reference line blref <0> according to the same principle, and at this time, the data stored in the cell can be judged by the potential difference between the bit line and the reference line. As shown in fig. 2, the equivalent circuit of the storage node bl0 is that a ferroelectric capacitor Ccell exists between the storage nodes bl0 and PL, the capacitance of the metal line of the bit line bl <0> is Cm, and the bit line bl <0> is connected with the word line wl0 through the transmission transistor, and the other word lines wl1 are connected through the transmission transistor, at this time, the potential of the word lines is 0, so that the bit line bl <0> and the part of the word lines have parasitic capacitance, and the capacitance is equivalent to Σcgs in fig. 2 because the capacitances are in parallel connection, thereby calculating the capacitance cbl=cm+cgs_i, i=0, …, n-1 of the storage node bl0, wherein n is the number of rows of the word lines; the voltage Vbl of storage node bl 0=vpl×ccell/(ccell+cbl), where Vbl is the bit line bl <0>, i.e. the voltage at storage node bl0, vpl is the voltage on plate line PL. Since the magnitude of the potential difference between the bit line and the reference line is usually measured directly, in practical applications, a sensing circuit is added between the bit line and the reference line, which includes a sense amplifier and a corresponding circuit, to differentially amplify the small signals on the bit line and the reference line into identifiable standard logical values of "1" and "0". In the conventional 2T2C ferroelectric memory structure, as shown in fig. 3, half of the bit lines are used as reference lines, so that one set of sensing circuits is required for each pair of bit lines, for example, 64 sets of sensing circuits are required if there are 128 bit lines, and in the 1T1C ferroelectric memory structure, as shown in fig. 4, a common reference line is provided, so that one set of sensing circuits is required for each bit line to be connected to the common reference line, for example, 128 sets of sensing circuits are required if there are 128 bit lines. As the capacity of the ferroelectric memory increases, the number of bit lines increases, and the number of sense amplifiers and sense circuits required for the ferroelectric memory increases, so that the volume of the ferroelectric memory increases exponentially, which is contrary to the development demands of miniaturization and high density of the ferroelectric memory.
Disclosure of Invention
In view of some or all of the problems in the prior art, an aspect of the present invention provides a ferroelectric memory, including:
each byte memory cell comprises a plurality of memory cells, each memory cell comprises a bit line and a plate line, and the plate lines of the byte memory cells are mutually independent; and
the first selection circuit comprises a plurality of first selection sub-circuit modules, one end of each first selection sub-circuit module is electrically connected to a bit line of a respective memory cell of each byte memory cell, the other end is connected to a plurality of corresponding sensing circuits,
the sensing circuit outputs a sensing signal according to an input signal of a bit line of a connected memory cell, and when a first selection sub-circuit module connected with any one byte memory cell is turned on, the first selection sub-circuit modules connected with the other byte memory cells are turned off, so that only the bit line of one byte memory cell is electrically connected to the sensing circuit at a time.
Further, the sensing circuit includes a plurality of sense amplifiers, and when a certain byte memory cell is selected, a first input terminal of each sense amplifier is electrically connected to a bit line of each memory cell of the byte memory cell in turn through a first selection sub-circuit module, and a second input terminal is electrically connected to a reference line corresponding to the bit line through the first selection sub-circuit module or directly.
Further, the first selection sub-circuit module includes a plurality of selection switches, one end of each of which is connected to one bit line, and the other end is connected to the sensing circuit.
Further, the selection switch includes:
an inverter having an input coupled to the selection signal generating circuit;
a first switching transistor having a gate coupled to the selection signal generating circuit; and
a second switching transistor having a gate coupled to an output of the inverter.
Further, the signal generating circuit includes:
a command decoder which encodes according to the storage control instruction to form a storage address;
and an address decoder, which is communicably connected to the command decoder, and decodes the memory address after receiving the memory address, and generates a selection signal.
Further, the ferroelectric memory further includes a plate line voltage generating circuit including:
a first transistor having a first terminal connected to an input voltage and a gate coupled to the first terminal;
the input end of the linear voltage stabilizing module is connected to the second end of the first transistor; and
the voltage dividing module is connected in series with the second end of the first transistor and is connected to the ground, wherein the first end of the first transistor refers to the source electrode or the drain electrode of the first transistor.
Further, the linear voltage stabilizing module comprises an operational amplifier, wherein the positive input end of the operational amplifier is connected to the second end of the first transistor, and the negative input end of the operational amplifier is connected to the output end of the amplifier; and/or
The voltage dividing module comprises a second transistor or resistor, a first end of the second transistor or resistor is connected to a second end of the first transistor, a second end of the second transistor or resistor is grounded, and a gate of the second transistor is coupled to a bias circuit, wherein the first end of the second transistor refers to a source or a drain of the first transistor.
Further, the ferroelectric memory further comprises a plurality of sectors, wherein each sector comprises N byte memory cells, all bit lines in each sector are connected to a plurality of bit line coupling lines in a one-to-one correspondence through one second selection subcircuit module, when the second selection subcircuit module corresponding to any sector is on, the second selection subcircuit modules corresponding to the other sectors are off, and the sensing circuit is connected to the bit line coupling lines through the first selection subcircuit module.
Further, the second selection sub-circuit module includes a plurality of the selection switches, and the bit lines are connected to the bit line coupling lines through the selection switches in a one-to-one correspondence.
Another aspect of the present invention provides a method of operating the ferroelectric memory, comprising:
according to the selection signal, controlling the corresponding second selection sub-circuit module to be conducted, and enabling the rest second selection sub-circuit modules to be turned off, wherein the bit line of the memory cell of one sector is connected to the bit line coupling line; and
and according to the selection signal, controlling the corresponding first selection sub-circuit modules to be conducted, and enabling the rest first selection sub-circuit modules to be turned off, wherein the bit line coupling line of the selected byte memory cell is connected to the sensing circuit to read and write the byte at the designated position.
The invention provides a ferroelectric memory, which is characterized in that a first selection circuit is added in the ferroelectric memory, so that each byte of memory cells in the ferroelectric memory share a group of sensing circuits, and particularly, the same bit of each byte shares a sense amplifier. In order to achieve this, in the present invention, each byte memory cell includes an independent plate line, and in order to ensure the read-write accuracy, the present invention also provides a plate line voltage generation circuit such that the plate line voltage is at least less than the supply voltage by Vt. Therefore, compared with the existing ferroelectric memory, the ferroelectric memory provided by the invention not only reduces the complexity of the circuit, but also saves a large amount of wiring space, so that the size of the ferroelectric memory is optimized, and the memory with larger capacity can be realized on a smaller size.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, for clarity, the same or corresponding parts will be designated by the same or similar reference numerals.
FIG. 1 shows a prior art read schematic of a ferroelectric memory;
FIG. 2 is a schematic diagram showing an equivalent circuit of a ferroelectric memory according to the prior art during reading;
FIG. 3 is a schematic diagram of a sensing circuit of a 2T2C structure memory according to the prior art;
FIG. 4 is a schematic diagram of a sensing circuit of a 1T1C structure memory according to the prior art;
FIG. 5 is a schematic diagram of a 2T2C ferroelectric memory according to one embodiment of the present invention;
FIG. 6 shows a schematic diagram of a sector of a ferroelectric memory of 2T2C structure according to one embodiment of the present invention;
FIG. 7 is a schematic diagram showing a partial structure of a ferroelectric memory with a 2T2C structure according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a 1T1C ferroelectric memory according to one embodiment of the present invention;
fig. 9 is a schematic diagram showing a structure of a selection switch of a ferroelectric memory according to an embodiment of the present invention; and
fig. 10 is a schematic diagram showing a plate line voltage generating circuit of a ferroelectric memory according to an embodiment of the present invention.
Detailed Description
In the following description, the present invention is described with reference to various embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention. Similarly, for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention is not limited to these specific details. Furthermore, it should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.
Reference throughout this specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
It should be noted that the embodiments of the present invention describe the process steps in a specific order, however, this is merely to illustrate the specific embodiment and not to limit the order of the steps. In contrast, in various embodiments of the present invention, the order of the steps may be adjusted according to process adjustments.
Aiming at the problem that the memory density is difficult to improve due to the large wiring space required by the sensing circuit in the prior art, the invention provides a ferroelectric memory, which greatly reduces the wiring space by sharing the sensing circuit. The embodiments of the present invention will be further described with reference to the drawings.
Fig. 5 shows a schematic diagram of a ferroelectric memory with a 2T2C structure according to an embodiment of the present invention.
As shown in fig. 5, for the ferroelectric memory of the 2T2C structure, it includes a plurality of byte memory cells, each byte memory cell includes 8 memory cells, each memory cell includes a pair of bit lines and plate lines, and the plate lines of the respective byte memory cells are independent from each other. As shown, each ferroelectric unit in each byte memory cell byte is connected with a plate line PL < k > corresponding to the byte memory cell, blk <8> is that blk <15> is respectively in one-to-one correspondence with blk <0>: blk <7>, reading and writing of each byte of 0-7 bits are realized, each bit line is connected to a sense amplifier in a sense circuit through a first selection circuit, the first selection circuit comprises a plurality of first selection sub-circuit modules, each first selection sub-circuit module is in one-to-one correspondence with each byte memory cell byte, and one first selection sub-circuit module is electrically connected with each bit line of each memory cell in one byte memory cell byte. In the embodiment of the present invention, the bit lines of the memory cells at the same position of each byte memory cell are respectively connected to the same sense amplifier through the first selection sub-circuit module corresponding to each byte memory cell, for example, bl0<0>, bl1<0>, … bl7<0> … of each byte memory cell are respectively connected to the positive input terminal of the first sense amplifier sa <0>, bl0<8>, bl1<8>, … bl7<8> … of each byte memory cell through the first selection sub-circuit module corresponding to each byte memory cell, are respectively connected to the negative input terminal of the first sense amplifier sa <0>, and so on until bl0<7>, bl1<7>, … bl7<7> … of each byte memory cell are respectively connected to the positive input terminal of the eighth sense amplifier sa <0>, bl 15 <15>, bl1<15> and the negative input terminal of each byte memory cell <15> through the first selection sub-circuit module corresponding to each byte memory cell, respectively. When any one of the first selection sub-circuit modules is turned on, the rest of the first selection sub-circuit modules are turned off, so that only bit lines of one byte memory cell are connected to the sensing circuit at a time, sharing of the sensing circuits is realized, only 8 groups of sensing circuits are needed in the whole ferroelectric memory, and if the ferroelectric memory comprises 128 bit lines, compared with the prior art, the number of the sensing circuits is reduced from 64 groups to 8 groups, the wiring space is greatly reduced, and the storage density is improved.
In one embodiment of the present invention, the first selection sub-circuit module includes a plurality of selection switches YAswitch, and all YAswitches in the same first selection sub-circuit module are closed or opened simultaneously. Each selection switch YA switch is connected to the bit line of the memory cell in each byte memory cell in a one-to-one correspondence manner, and for the structure shown in fig. 5, each first selection sub-circuit module includes 16 selection switches YA switches, which are respectively connected to 16 bit lines in one byte memory cell.
Fig. 9 is a schematic diagram showing a structure of a selection switch of a ferroelectric memory according to an embodiment of the present invention. As shown in fig. 9, the selection switch YA switch includes a first switching transistor M1, a second switching transistor M2, and an inverter F1, wherein: an input end of the inverter F1 is coupled to a selection signal generation circuit; the first switch transistor M1 has a source-drain path and a gate, the source-drain path of the first switch transistor M1 is connected between the bit line bl and a sensing circuit, and the gate of the first switch transistor M1 is coupled to a selection signal generating circuit; the second switching transistor M2 has a source-drain path and a gate, the source-drain path of the second switching transistor M2 is connected between the bit line bl and the sensing circuit, and the gate of the second switching transistor M2 is coupled to the output terminal of the inverter F1. When a certain byte memory cell is selected, the connected selection signal is high, and the first switch transistor and the second switch transistor are both turned on. The second switching transistor M2 is used as a redundancy transistor of the first switching transistor M1, and is turned on in a redundancy manner when the first switching transistor is damaged, so that the operation of the memory cell is not affected. The selection signal generating circuit is used for determining a storage address according to a storage control instruction, the selection signal generating circuit comprises a command decoder and an address decoder, the command decoder is used for encoding according to the storage control instruction to form the storage address and sending the storage address to the address decoder, and the address decoder is used for decoding after receiving the storage address to generate a selection signal.
In one embodiment of the present invention, the ferroelectric memory is further divided into a plurality of sectors in order to avoid the limitation of the number of bit line connection word lines. Fig. 6 shows a schematic diagram of a sector of a 2T2C structure ferroelectric memory according to one embodiment of the present invention. As shown in fig. 6, a 2T2C structure ferroelectric memory includes a plurality of sectors (sectors), and each sector includes 128 word lines WL and a plurality of byte memory cells, each byte memory cell includes 16 bit lines bl and 1 plate line, and the bit lines are coupled to a bit line coupling line sabl through a second selection circuit. In one embodiment of the present invention, the second selection circuit includes a plurality of second selection sub-circuit modules, and the second selection sub-circuit modules include a plurality of selection switches sector switches, the number of the selection switches sector switches is consistent with the number of bit lines included in the sectors, when the second selection sub-circuit module corresponding to any sector is turned on, all the selection switches sector switches included in the second selection sub-circuit module corresponding to any sector are turned on, and the second selection sub-circuit modules corresponding to the other sectors are turned off. The selector switch has the same structure as the YA switch, and as shown in fig. 9, the selector switch includes a first switch transistor, a second switch transistor and an inverter, where: an input terminal of the inverter is coupled to a selection signal generation circuit; the first switch transistor has a source-drain path and a gate, the source-drain path of the first switch transistor is connected between the bit line and the bit line coupling line, the gate of the first switch transistor is coupled to the selection signal generating circuit; the second switching transistor has a source-drain path connected between the bit line and the bit line coupling line and a gate coupled to an output of the inverter. When a certain sector is selected, the connected selection signal is high, and the first switching transistor and the second switching transistor are both turned on. The second switching transistor is used as a redundant transistor of the first switching transistor, and redundant conduction is realized when the first switching transistor is damaged, so that the operation of the memory cell is not influenced.
To more clearly describe the scheme of the present invention, fig. 7 shows a schematic partial structure of a 2T 2C-structure ferroelectric memory according to one embodiment of the present invention. The byte memory cells byte include a plurality of memory cells arranged in a matrix structure of i rows and j columns, wherein each memory cell is connected to a plate line PL < k > corresponding to the memory cell of the present byte, the memory cells of the i-th row are connected to a word line wl < i > corresponding to the present row, and the memory cells of the j-th column are connected to a bit line bl < j > corresponding to the present column. In one embodiment of the invention, the byte memory locations byte include 128 rows and 16 columns of memory locations. Wherein the memory cell comprises a ferroelectric capacitor and a transistor, wherein the ferroelectric capacitor has a first plate and a second plate, the first plate is connected to a plate line, each byte memory cell has an independent plate line, as shown in fig. 8, sector <0> -PL <0> -bl <15> refers to a plate line PL <0> of a first byte memory cell byte0 in a first sector <0>, wherein all of bl <0> to bl <15> of the byte memory cell are connected to the plate line PL <0>, sector <1> -bl <0> tobl > refer to a plate line PL <0> of the first byte memory cell byte0 in a second sector <1>, wherein all of bl <0> to bl <15> of the byte memory cell are connected to the plate line PL <0>, and so on; and the source-drain electrode path of the transistor is connected between the second polar plate and the bit line corresponding to the column, and the grid electrode is coupled to the word line corresponding to the row. As shown in fig. 8, each bit line is connected to a bit line coupling line through a sector switch, specifically, a bit line bl <0> is connected to a positive input terminal of a first sense amplifier SALAT <0> through a sector switch, a bit line bl <1> is connected to a bit line coupling line SABLE <1> through a sector switch, a positive input terminal of a second sense amplifier SALAT <1> through a sector switch, and so on, until a bit line bl <7> is connected to a bit line coupling line SABLE <7> through a sector switch, a positive input terminal of an eighth sense amplifier SALAT 7> through a sector switch, and a bit line bl <8> is connected to a positive input terminal of a bit line coupling amplifier, a negative input terminal of a bit line coupling amplifier is connected to a positive input terminal of a bit line coupling amplifier SABLE <1> through a sector switch, a positive input terminal of a bit line coupling amplifier is connected to a bit line coupling amplifier <1> through a sector switch, a positive input terminal of a bit line coupling amplifier is connected to a positive input terminal of a bit line coupling amplifier, and a negative input terminal of a bit line coupling amplifier is connected to a bit line coupling 1 through a sector switch, a positive input terminal of a coupling of a bit line coupling of a 2 is connected to a bit line coupling of a positive input terminal of a bit amplifier is connected to a bit line coupling of a 1, and a bit amplifier is connected to a positive input terminal of a bit line coupling of a bit amplifier.
Fig. 8 shows a schematic diagram of a ferroelectric memory with a 1T1C structure according to an embodiment of the present invention. It is similar to the ferroelectric memory structure of the 2T2C structure, except that in the ferroelectric memory of the 1T1C structure, the number of bit lines of each memory cell is 1, each memory cell in each byte memory cell is connected to the plate line PL < k > corresponding to the memory cell of the byte, the bit line bl <0> is connected to the positive input terminal of the first sense amplifier salat <0> through the switch, the bit line bl <1> is connected to the positive input terminal of the second sense amplifier salat <1> through the switch, and so on until the bit line bl <7> is connected to the positive input terminal of the eighth sense amplifier salat <7>, the negative input terminal of each sense amplifier is connected to the reference voltage line, and as can be seen, through the cooperation of the switch, the sense circuit is shared, so that in the whole ferroelectric memory, only 8 groups of sense circuits are needed, and the number of sense circuits is reduced from the prior art 128 groups of sense circuits, if the number of sense circuits is increased from the prior art 128 to the prior art. Likewise, the ferroelectric memory may be further divided into a plurality of sectors by a second selection circuit.
In the embodiment of the invention, as each byte memory cell shares the sensing circuit, only one byte memory cell is connected with the sensing circuit at a time to realize read-write operation, so that each byte memory cell needs to have an independent plate line and a corresponding plate line voltage generating circuit.
The read-write of the ferroelectric memory is realized by forming electric fields in different directions on the ferroelectric capacitance mainly through the coordination of bit lines and plate lines. To avoid that the voltage at the other end of the ferroelectric capacitor is lower than Vpl when Vpl is high, thus creating an electric field inconsistent with the requirements, it is often necessary to pull the word line voltage up by at least one Vt. However, if a higher voltage needs to be generated, the required circuit is complex, and a series of components such as a charge pump or booster, a bandgap reference voltage source (bandgap), and a low dropout linear regulator LDO are required, and at the same time, a large amount of power is consumed. In response to this problem, in one embodiment of the present invention, a PL voltage Vpl smaller than the supply voltage Vcc is generated by a plate line voltage generating circuit to ensure the electric field direction and thus the read-write accuracy. Fig. 10 is a schematic diagram showing a plate line voltage generating circuit of a ferroelectric memory according to an embodiment of the present invention. As shown in fig. 10, the board-line voltage generating circuit includes a first transistor M3, a low dropout linear voltage regulator module, and a voltage divider module, wherein a first terminal of the first transistor M3 is connected to a supply voltage Vcc, a gate thereof is coupled to the first terminal, and an input terminal of the linear voltage regulator module is connected to a second terminal of the first transistor; the voltage dividing module is connected in series to the second end of the first transistor and grounded, wherein the first end of the first transistor M3 refers to the source or the drain of the first transistor. In one embodiment of the present invention, the linear voltage stabilizing module includes an operational amplifier OP, wherein a positive input terminal of the operational amplifier OP is connected to the second terminal of the first transistor M3, and a negative input terminal of the operational amplifier OP is connected to an output terminal of the operational amplifier OP. In one embodiment of the present invention, the voltage dividing module includes a second transistor M4, a first terminal of the second transistor M4 is connected to a second terminal of the first transistor, a second terminal is grounded, and a gate is coupled to the bias circuit nbias, wherein the first terminal of the second transistor M4 refers to a source or a drain of the second transistor. It should be appreciated that in other embodiments of the present invention, the voltage dividing module may also include a resistor, where a first end of the resistor is connected to a second end of the first transistor, and the second end is grounded. Other LDO devices or circuits may be used for the linear voltage regulator module.
The invention provides a ferroelectric memory, which is characterized in that a first selection circuit is added in the ferroelectric memory, so that each byte of memory cells in the ferroelectric memory share a group of sensing circuits, and particularly, the same bit of each byte shares a sense amplifier. In order to achieve this function, in the present invention, each byte memory cell includes an independent plate line, and in order to ensure the correctness of reading and writing, the present invention also provides a plate line voltage generating circuit such that the plate line voltage is at least 1 Vt smaller than the power supply voltage. When performing read-write operation, firstly, the selection signal generating circuit analyzes the storage control instruction to obtain address information, then, according to the address information, the second selection circuit is controlled to select a corresponding sector (sector), and then, the first selection circuit is controlled to select a corresponding byte storage unit, so that the read-write operation is realized byte by byte. Compared with the existing ferroelectric memory, the ferroelectric memory provided by the invention not only reduces the complexity of the circuit, but also can save a large amount of wiring space, so that the size of the ferroelectric memory is optimized, and the memory with larger capacity can be realized on a smaller size.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to those skilled in the relevant art that various combinations, modifications, and variations can be made therein without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention as disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims (9)
1. A ferroelectric memory, comprising:
a plurality of byte memory cells, wherein each byte memory cell comprises a plurality of memory cells, each memory cell comprises a bit line and a plate line, and the plate lines of the byte memory cells are mutually independent; and
the first selection circuit comprises a plurality of first selection sub-circuit modules, one end of each first selection sub-circuit module is electrically connected to a bit line of each storage unit of each byte storage unit, and the other end is connected to a plurality of corresponding sensing circuits, wherein:
the sensing circuit comprises a plurality of sense amplifiers, bit lines of memory cells in the same position of each byte memory cell are respectively connected to the same sense amplifier through first selection subcircuit modules corresponding to the memory cells of each byte, the sensing circuit outputs a sensing signal according to input signals of the bit lines of the connected memory cells, when a certain byte memory cell is selected, a first input end of each sense amplifier is sequentially and electrically connected to the bit lines of the memory cells of the selected byte memory cell through the first selection subcircuit modules, and a second input end of each sense amplifier is directly and electrically connected to a reference line corresponding to the bit lines through the first selection subcircuit modules.
2. The ferroelectric memory of claim 1 wherein said first selection subcircuit module comprises a plurality of selection switches, each selection switch having one end connected to a bit line and the other end connected to a sense circuit.
3. The ferroelectric memory of claim 2 wherein said selection switch comprises:
an inverter having an input coupled to the selection signal generating circuit;
a first switching transistor having a gate coupled to the selection signal generating circuit; and
a second switching transistor having a gate coupled to an output of the inverter.
4. The ferroelectric memory of claim 3 wherein said signal generating circuit comprises:
a command decoder configured to encode according to a storage control instruction, forming a storage address; and
an address decoder, communicatively coupled to the command decoder, is configured to decode upon receipt of the memory address, generating a select signal.
5. The ferroelectric memory of claim 1, further comprising a plate line voltage generation circuit, the plate line voltage generation circuit comprising:
a first transistor having a first terminal connected to an input voltage and a gate coupled to the first terminal;
the input end of the linear voltage stabilizing module is connected to the second end of the first transistor; and
the voltage dividing module is connected in series with the second end of the first transistor and is connected to the ground, wherein the first end of the first transistor refers to the source electrode or the drain electrode of the first transistor.
6. The ferroelectric memory of claim 5, wherein said linear voltage regulator module comprises an operational amplifier having a positive input connected to said first transistor second terminal and a negative input connected to said amplifier output; and/or
The voltage dividing module comprises a second transistor or resistor, a first end of the second transistor or resistor is connected to a second end of the first transistor, a second end of the second transistor or resistor is grounded, and a gate of the second transistor is coupled to a bias circuit, wherein the first end of the second transistor refers to a source or a drain of the first transistor.
7. The ferroelectric memory of any one of claims 1-6, further comprising a plurality of sectors, wherein each of the sectors comprises N byte memory cells, all bit lines in each sector are connected to a plurality of bit line coupling lines in a one-to-one correspondence by one second selection subcircuit module, and when the second selection subcircuit module corresponding to any one sector is turned on, the second selection subcircuit modules corresponding to the remaining sectors are turned off, and the sensing circuit is connected to the bit line coupling lines by the first selection subcircuit module.
8. The ferroelectric memory of claim 7, wherein said second selection subcircuit module comprises a plurality of selection switches through which said bit lines are connected to bit line coupling lines in a one-to-one correspondence, wherein said selection switches comprise:
an inverter having an input coupled to the selection signal generating circuit;
a first switching transistor having a gate coupled to the selection signal generating circuit; and
a second switching transistor having a gate coupled to an output of the inverter.
9. A method of operating a ferroelectric memory as claimed in claim 7, comprising the steps of:
according to the selection signal, controlling the corresponding second selection sub-circuit module to be conducted, and enabling the rest second selection sub-circuit modules to be turned off, wherein the bit line of the memory cell of one sector is connected to the bit line coupling line; and
and according to the selection signal, controlling the corresponding first selection sub-circuit modules to be conducted, and enabling the rest first selection sub-circuit modules to be turned off, wherein the bit line coupling line of the selected byte memory cell is connected to the sensing circuit to read and write the byte at the designated position.
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| CN113808639B (en) * | 2021-09-24 | 2023-07-07 | 电子科技大学 | Ferroelectric memory cell read-write characteristic verification circuit structure |
| CN116959525A (en) * | 2022-04-20 | 2023-10-27 | 华为技术有限公司 | Bit line reading circuit, memory and electronic equipment |
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