CN111402939A - Ferroelectric memory and method of operating the same - Google Patents
Ferroelectric memory and method of operating the same Download PDFInfo
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- CN111402939A CN111402939A CN202010222158.9A CN202010222158A CN111402939A CN 111402939 A CN111402939 A CN 111402939A CN 202010222158 A CN202010222158 A CN 202010222158A CN 111402939 A CN111402939 A CN 111402939A
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- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
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- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
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- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
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Abstract
The invention relates to a ferroelectric memory comprising: a plurality of ferroelectric memory cells including a ferroelectric capacitor including upper and lower plates and a ferroelectric material between the upper and lower plates; a write circuit configured to be able to apply a first voltage and a second voltage to two plates of a ferroelectric capacitor of a ferroelectric memory cell in forward and reverse directions, respectively, so that the ferroelectric material has corresponding first, second, third and fourth remnant polarization values, respectively, to write different stored data; and the reading circuit comprises a reference voltage generating circuit and a voltage comparison circuit, wherein the voltage comparison circuit can compare the acquired voltage at one end of the ferroelectric capacitor of the ferroelectric memory cell with the reference voltage generated by the reference voltage generating circuit to output different comparison results so as to read different storage data. By the invention, the storage of 2-bit data per storage unit can be realized, thereby greatly improving the storage density and the storage capacity.
Description
Technical Field
The present invention relates generally to the field of semiconductors, and more particularly to a ferroelectric memory. The invention further relates to a method for operating such a ferroelectric memory.
Background
In recent years, as a new memory with high writing speed and high read-write times, a ferroelectric memory is increasingly used as a nonvolatile memory with a special process. When an electric field is applied to a ferritransistor, the central atom stops at a first low energy state position along the electric field, and when an electric field reversal is applied to the same ferritransistor, the central atom moves in the crystal along the direction of the electric field and stops at a second low energy state. A large number of central atoms move and couple in the crystal unit cell to form a ferroelectric domain, and the ferroelectric domain forms polarization charges under the action of an electric field. The polarization charge formed by the ferroelectric domain reversing under the electric field is higher, and the polarization charge formed by the ferroelectric domain not reversing under the electric field is lower, so that the binary stable state of the ferroelectric material can lead the ferroelectric to be used as a memory.
When the electric field is removed, the central atom is in a low energy state and remains unchanged, and the state of the memory is also preserved and does not disappear, so that the ferroelectric domain can be used for forming high polarization charges by inversion under the electric field or forming low polarization charges without inversion to judge that the memory cell is in a '1' or '0' state. The inversion of the ferroelectric domain does not need high electric field, and the state of the memory cell in '1' or '0' can be changed only by using common working voltage; and a charge pump is not needed to generate high voltage for data erasing, so that the phenomenon of erasing delay is avoided. The characteristic enables the ferroelectric memory to still keep data after power failure, has high writing speed and infinite writing service life, and is not easy to be damaged. And, compared with the existing non-volatile memory technology, the ferroelectric memory has higher writing speed and longer read-write life.
In current ferroelectric memories, each memory cell stores 1 bit of data, i.e., 0 or 1. If more bits per memory cell can be realized, the storage density or storage capacity of the ferroelectric memory can be greatly increased.
Disclosure of Invention
The object of the present invention is to provide a ferroelectric memory and a method for operating the same, by means of which a storage of 2-bit data per ferroelectric memory cell can be achieved, whereby the storage density and the storage capacity are greatly increased.
In a first aspect of the present invention, this object is achieved by a ferroelectric memory comprising:
a plurality of ferroelectric memory cells, each ferroelectric memory cell comprising a ferroelectric capacitor comprising an upper plate and a lower plate and a ferroelectric material between the upper plate and the lower plate;
a write circuit configured to apply a first voltage and a second voltage to two plates of a ferroelectric capacitor of a ferroelectric memory cell in forward and reverse directions, respectively, so that the ferroelectric material has corresponding first, second, third and fourth remnant polarization values, respectively, to write different stored data, wherein the different remnant polarization values correspond to the different stored data; and
and the reading circuit comprises a reference voltage generating circuit and a voltage comparison circuit, wherein the voltage comparison circuit can compare the acquired voltage at one end of the ferroelectric capacitor of the ferroelectric memory cell with the reference voltage generated by the reference voltage generating circuit to output different comparison results so as to read different storage data.
In a preferred embodiment of the present invention, it is provided that the values of the third remanent polarization and the fourth remanent polarization corresponding to the second voltage applied to the ferroelectric capacitor by the write circuit are 1/3 times the values of the first remanent polarization and the second remanent polarization corresponding to the first voltage applied to the ferroelectric capacitor by the write circuit.
In a preferred embodiment of the present invention, it is provided that the write circuit includes first, second, third and fourth and gates, wherein two inputs of the first and gate input the inverted values of the most significant bit and the least significant bit of the signal to be written, respectively, and an output thereof is connected to one of the inputs of the first nand gate, an input of the second and gate inputs the most significant bit and the least significant bit of the signal to be written, respectively, and an output thereof is connected to one of the inputs of the second nand gate, an input of the third and gate inputs the inverted value of the most significant bit and the least significant bit of the signal to be written, respectively, an output thereof is connected to one of the inputs of the third nand gate, and an input of the fourth and gate inputs the inverted value of the most significant bit and the inverted value of the least significant bit of the signal to be written, respectively, and an output thereof is connected to one of the inputs of the;
the first NAND gate, the second NAND gate, the third NAND gate and the fourth NAND gate, wherein the other input end of the first NAND gate, the second NAND gate, the third NAND gate and the fourth NAND gate respectively inputs a write enable signal; and
a first transistor, a second transistor, a third transistor and a fourth transistor, wherein the grid of the first transistor is connected with the output end of the first NAND gate, one of a drain and a source thereof is connected to a first voltage, and the other of the drain and the source thereof is connected to a bit line of the ferroelectric memory cell to be written, a gate of the second transistor is connected to an output terminal of the second nand gate, one of a drain and a source thereof is connected to a second voltage, and the other of the drain and the source thereof is connected to a bit line of the ferroelectric memory cell to be written, a gate of the third transistor is connected to an output terminal of the third nand gate, one of a drain and a source thereof is connected to a third voltage, and the other of the drain and the source thereof is connected to a bit line of the ferroelectric memory cell to be written, a gate of the fourth transistor is connected to an output terminal of the fourth nand gate, one of a drain and a source thereof is connected to a fourth voltage, and the other of the drain and the source thereof is connected to a bit line of the ferroelectric memory cell to be written.
In a preferred embodiment of the invention, the read circuit comprises:
four reference cells configured to generate first, second, third and fourth bit line voltages on bit lines thereof corresponding to 00, 01, 10, 11, respectively, in case of being written to one of 00, 01, 10, 11, respectively, wherein the first, second, third and fourth bit line voltages are sequentially raised;
a first reference voltage generating circuit for generating a first reference voltage according to the first and second bit line voltages, wherein the magnitude of the first reference voltage is between the magnitudes of the first and second bit line voltages;
the second reference voltage generating circuit generates a second reference voltage according to the second bit line voltage and the third bit line voltage, wherein the magnitude of the second reference voltage is between the magnitude of the second bit line voltage and the magnitude of the third bit line voltage; and
the third reference voltage generation circuit generates a third reference voltage according to the third and fourth bit line voltages, wherein the magnitude of the third reference voltage is between the magnitudes of the third and fourth bit line voltages.
In a preferred embodiment of the invention, it is provided that the first reference voltage is an average of a sum of the first bit line voltage and the second bit line voltage, the second reference voltage is an average of a sum of the second bit line voltage and the third bit line voltage, and the third reference voltage is an average of a sum of the third bit line voltage and the fourth bit line voltage.
In a preferred embodiment of the present invention, it is provided that the voltage comparison circuit comprises three voltage comparators, wherein a first voltage comparator has one input connected to a first reference voltage and another input connected to a bit line of the ferroelectric memory cell; one input end of the second voltage comparator is connected with a second reference voltage, and the other input end of the second voltage comparator is connected with a bit line of the ferroelectric memory unit; one input end of the third voltage comparator is connected with a third reference voltage, and the other input end of the third voltage comparator is connected with a bit line of the ferroelectric memory unit.
In a preferred embodiment of the present invention, it is provided that the voltage comparison circuit includes a voltage selection circuit and a voltage comparator, wherein three input terminals of the voltage selection circuit input one of the three reference voltages output by the reference voltage generation circuit, respectively, and an output terminal thereof is connected to one input terminal of the voltage comparator,
the other input end of the voltage comparator is connected with the bit line of the ferroelectric memory unit, and the output end of the voltage comparator outputs a comparison result;
the voltage comparison circuit also comprises a voltage comparator clock signal control circuit which comprises a delay circuit and a NOT gate, wherein the input end of the delay circuit is connected with the output end of the voltage comparator, and the output end of the NOT gate is connected with the clock signal input end of the voltage comparator.
In a preferred embodiment of the present invention, it is provided that the output terminal of the voltage comparator includes a first output terminal and a second output terminal, and the first output terminal and the second output terminal output a comparison ready signal through a nand gate; the reading circuit further comprises a control signal generating circuit, wherein the control signal generating circuit comprises a shift register formed by two D triggers which are connected with each other, the output end of the first D trigger is connected with the control signal input end of the voltage selection circuit, and the output end of the second D trigger is connected with the input end of the clock signal control circuit of the voltage comparator.
In a preferred aspect of the present invention, it is provided that the read circuit further comprises a read signal latch circuit including a third D flip-flop for latching the most significant bit of the read signal, and a fourth D flip-flop for latching the least significant bit of the read signal; the output end of the voltage comparator is connected with the input ends of the third D trigger and the fourth D trigger, the reverse signal for starting reading is connected with the reset ends of the third D trigger and the fourth D trigger, the output end of the first D trigger is connected with the clock signal end of the third D trigger, and the output end of the second D trigger is connected with the clock signal end of the fourth D trigger.
In a second aspect of the invention, the aforementioned task is fulfilled by a method of writing a ferroelectric memory according to the invention, the method comprising
And applying a first voltage and a second voltage to two polar plates of a ferroelectric capacitor of the ferroelectric memory unit respectively in a forward direction and a reverse direction by using the write-in circuit, so that the ferroelectric material respectively has corresponding first, second, third and fourth remnant polarization values, and different storage data respectively corresponding to different remnant polarization values is written in.
In a preferred embodiment of the invention, it is provided that the method further comprises:
three reference voltages are generated with the read circuit,
and comparing the bit line voltage of the ferroelectric memory cell acquired by the reading circuit with the three reference voltages respectively, and reading data stored in the ferroelectric memory cell according to the comparison result.
In a preferred embodiment of the invention, it is provided that the method further comprises:
generating three reference voltages by using the reading circuit, wherein the third reference voltage is greater than the second reference voltage, and the second reference voltage is greater than the first reference voltage;
comparing a bit line voltage of a ferroelectric memory cell to be read with a second reference voltage to obtain a first comparison result, and taking the first comparison result as a most significant bit of the read result; and
if the first comparison result is that the bit line voltage of the ferroelectric memory cell is greater than the second reference voltage, the bit line voltage is compared with a third reference voltage to obtain a second comparison result and the second comparison result is taken as the least significant bit of the read result, and if the first comparison result is that the bit line voltage of the ferroelectric memory cell is less than the second reference voltage, the bit line voltage is compared with the first reference voltage to obtain a third comparison result and the third comparison result is taken as the least significant bit of the read result.
The ferroelectric memory has the advantages that different voltages are applied to the ferroelectric memory units, different storage data are represented by different polarization strengths of ferroelectric materials, each storage unit stores multi-bit data, the storage density of the ferroelectric memory can be improved, and the storage capacity of the unit area of the ferroelectric memory is improved. Meanwhile, the invention designs a new writing circuit and a new reading circuit of the ferroelectric memory, and the data of the ferroelectric memory unit is read and written through the writing circuit and the reading circuit. The write circuit and the read circuit are simple in structure, occupy small chip structure size and can reduce the size of a memory.
Drawings
The invention is further elucidated with reference to the drawings in conjunction with the detailed description.
Fig. 1 is a schematic structural view of one ferroelectric memory cell of the ferroelectric memory of the present invention.
Fig. 2 is a schematic diagram of the characterization principle of the stored data of the ferroelectric memory of the present invention.
Fig. 3 is a schematic diagram of a ferroelectric hysteresis loop for storing two bits of data per memory cell of the ferroelectric memory of the present invention.
FIG. 4A is a schematic diagram showing a reference voltage generating circuit at the time of reading data of the ferroelectric memory according to the present invention
FIG. 4B is a diagram showing the values of bit line voltages when storing different data and different reference voltages when reading data according to the ferroelectric memory of the present invention;
fig. 5 is a schematic diagram of a read data voltage comparison circuit according to an embodiment of the present invention, in which three comparators are used for comparison at the same time.
FIG. 6 is a schematic diagram of a read data voltage comparison circuit according to another embodiment of the present invention, in which two comparisons are performed by using one comparator.
Fig. 7A is a schematic diagram of a data read compare circuit using the method shown in fig. 6.
Fig. 7B is a schematic diagram of the circuit for generating the control signals CK1 and CK2 in fig. 7A.
FIG. 7C is a schematic diagram of a read signal output circuit according to the embodiment in FIG. 7A.
FIG. 7D is a read control timing diagram according to the embodiment in FIG. 7A.
Fig. 8A is a schematic structural diagram of a data writing circuit according to an embodiment of the present invention.
FIG. 8B is a schematic diagram of a voltage signal generating circuit of the write circuit of FIG. 8A.
FIG. 8C is a schematic diagram of a control signal generating circuit of the write circuit of FIG. 8A.
Fig. 8D is a timing chart of write control of the write circuit in fig. 8A.
Detailed Description
It should be noted that the components in the figures may be exaggerated and not necessarily to scale for illustrative purposes. In the figures, identical or functionally identical components are provided with the same reference symbols.
In the present invention, "disposed on …", "disposed over …" and "disposed over …" do not exclude the presence of an intermediate therebetween, unless otherwise specified. Further, "disposed on or above …" merely indicates the relative positional relationship between two components, and may also be converted to "disposed below or below …" and vice versa in certain cases, such as after reversing the product direction.
In the present invention, the embodiments are only intended to illustrate the aspects of the present invention, and should not be construed as limiting.
In the present invention, the terms "a" and "an" do not exclude the presence of a plurality of elements, unless otherwise specified.
It is further noted herein that in embodiments of the present invention, only a portion of the components or assemblies may be shown for clarity and simplicity, but those of ordinary skill in the art will appreciate that, given the teachings of the present invention, required components or assemblies may be added as needed in a particular scenario.
It is also noted herein that, within the scope of the present invention, the terms "same", "equal", and the like do not mean that the two values are absolutely equal, but allow some reasonable error, that is, the terms also encompass "substantially the same", "substantially equal". By analogy, in the present invention, the terms "perpendicular", "parallel" and the like in the directions of the tables also cover the meanings of "substantially perpendicular", "substantially parallel".
The numbering of the steps of the methods of the present invention does not limit the order of execution of the steps of the methods. Unless specifically stated, the method steps may be performed in a different order.
The invention is further elucidated with reference to the drawings in conjunction with the detailed description.
As shown in fig. 1, a ferroelectric memory cell 100 of a ferroelectric memory according to the present invention has a ferroelectric capacitor 101 and a transistor 102, the ferroelectric capacitor 101 has two plates and a ferroelectric material sandwiched between the plates, the capacitor 101 has one end connected to a plate line P L and the other end connected to one of a drain and a source of the transistor 102, a gate of the transistor 102 is connected to a word line W L, and the other of the drain and the source thereof is connected to a bit line B L.
Because of the characteristics of the ferroelectric material, when an electric field is applied to the ferroelectric capacitor containing the ferroelectric material, the ferroelectric domains of the ferroelectric material will be polarized, and when the applied electric field is removed, the ferroelectric domains of the ferroelectric material will maintain a certain polarization degree, i.e. remanent polarization.
Referring to FIG. 2, in the read/write circuit 200, the potential of the bit line B L is measured by a collecting capacitor 201 connected to the bit line B L, and the potential of B L is converted into a digital signal 1 or 0 by an analog-to-digital converter 202, and then the data stored in the ferroelectric memory cell is characterized by comparing the signal of the potential of B L with a reference signal.
Referring to fig. 3, two different voltages VCC1 and VCC2 are applied to the capacitor 101 of the ferroelectric memory cell in the forward and reverse directions, respectively, in the ferroelectric memory of the present invention, because the applied voltages are different and the remanent polarization of the ferroelectric material of the ferroelectric memory cell is different, the ferroelectric hysteresis loop 300 corresponding to the two voltages of the ferroelectric memory cell will form two ferroelectric hysteresis loops, i.e., the first ferroelectric hysteresis loop 301 and the second ferroelectric hysteresis loop 302 in fig. 3. The intersection point of the ferroelectric hysteresis loop and the longitudinal axis is the residual polarization Pr of the ferroelectric material, and different logic storage signals are represented by different residual polarization Pr of the ferroelectric material.
In this embodiment, the first hysteresis loop 301 and the Pr axis have first and second intersection points D and a having first and second polarization intensity values, respectively, which represent "00" and "01" in the 2-bit data value, respectively, in this embodiment; the second hysteresis loop 202 has third and fourth intersections H and G with the Pr axis, which have third and fourth polarized intensity values, respectively, which represent "10" and "11" in the 2-bit data value, respectively, in the present embodiment. For this reason, the ferroelectric memory cell preferably has a sufficiently large Pr window, i.e., a large area of the ferroelectric hysteresis loop. The Pr window of the material can be increased through optimization of the material, meanwhile, the minimum sensible Pr window interval can be reduced through improving the precision of the reading circuit, the polarization degree difference of the ferroelectric material is caused by applying different voltages, and different data can be read out in the same reading mode through the polarization difference. And 2-bit read-write operation is realized. The ferroelectric material or the ferroelectric itself may have a plurality of hysteresis loops (such as the first and second hysteresis loops described herein), that is, the ferroelectric material or the ferroelectric has different hysteresis loops depending on different voltages applied. It should be noted here, however, that in the case of ferroelectric memory cells with smaller Pr windows, the present invention can still be implemented, except that since the four intersections (polarization values) are relatively close together, a more accurate read decision manner and write manner are required to achieve the distinction between the smaller polarization values.
In this embodiment of the invention, the value of the voltage VCC1 and the value of VCC2 applied to the ferroelectric capacitor are such that the absolute value of the third polarization intensity value ("01") is 1/3, i.e., 1/3Pr, of the absolute value of the first polarization intensity value ("00"), and the absolute value of the fourth polarization intensity value ("10") is 1/3, i.e., 1/3Pr, of the absolute value of the second polarization intensity value ("11"). By the arrangement, a larger margin can be realized during data reading/writing, so that error writing or error reading is avoided better.
Different voltages are respectively applied to the ferroelectric capacitors, then the applied voltages are cancelled, and different logic storage signals are represented by the residual polarization strength of the ferroelectric materials of the ferroelectric capacitors, so that the four values of '00', '01', '10' and '11' of the ferroelectric memory are written. Here, different voltages applied to the ferroelectric capacitor, i.e., a first voltage Vcc2, a second voltage Vcc1, a third voltage-Vcc 1, and a fourth voltage-Vcc 2 are shown on the abscissa, respectively. The absolute value of the first voltage is greater than the absolute value of the second voltage, and the absolute value of the fourth voltage is greater than the absolute value of the third voltage. Where negative voltage means that the voltage applied across the two plates of the ferroelectric capacitor is the opposite of the voltage applied to the positive voltage.
The ferroelectric memory utilizes the remnant polarization of ferroelectric material in the ferroelectric capacitor to affect the bit connected with one end of the ferroelectric capacitorThe ferroelectric memory of the present invention can store 2 bits of data per memory cell, and can have four states of 00, 01, 10 and 11, and the bit line voltages of the corresponding memory cells are respectively VB L00、VBL01、VBL10、VBL11To determine the specific data stored, three reference voltages need to be set and compared to the bit line voltage of the memory cell to determine the specific data stored.
Referring to FIG. 4A, a reference voltage generation circuit 400 is shown for setting three reference voltages, namely, for writing data 00, 01, 10, 11 into four reference cells (not shown) respectively, so as to generate first, second, third and fourth bit line voltages VB L corresponding to 00, 01, 10, 11 respectively on bit lines of the reference cells00、VBL01、VBL10、VBL11Wherein the first, second, third and fourth bit line voltages VB L00、VBL01、VBL10、VBL11Sequentially increasing;
the reference voltage generating circuit 400 generates the reference voltage according to the first and second bit line voltages VB L00、VBL01Generating a first reference voltage VREF1Wherein the first reference voltage VREF1Is between the magnitudes of the first and second bit line voltages, where the first reference voltage is 1/2 of the sum of the first and second bit line voltages, i.e., VREF1＝(VBL00+VBL01)/2。
From the second and third bit line voltages VB L by the reference voltage generating circuit 40001、VBL10Generating a second reference voltage VREF2Wherein the second reference voltage VREF2Is between the magnitudes of the second and third bit line voltages, where the second reference voltage is 1/2 of the sum of the second and third bit line voltages, i.e., VREF2＝(VBL01+VBL10)/2。
From a reference voltageThe generating circuit 400 generates the third and fourth bit line voltages VB L according to the voltage10、VBL11Generating a third reference voltage VREF3Wherein the third reference voltage VREF3Is between the magnitudes of the third and fourth bit line voltages, where the third reference voltage is 1/2 of the sum of the third and fourth bit line voltages, i.e., VREF3＝(VBL10+VBL11)/2。
The reference voltage generation circuit 400 may be constituted by, for example, an adder and a divider, and other ways are also conceivable.
As shown in fig. 4B, the first, second and third reference voltages VREF1、VREF2、VREF3And each bit line voltage VB L00、VBL01、VBL10、VBL11Thus, when the bit line voltage VB L of the memory cell is applied00、VBL01、VBL10、VBL11When the voltage value of the bit line of the memory cell is compared with the reference voltage, the voltage value of the bit line of the memory cell can be judged, and therefore the data stored by the memory cell can be determined.
Because the bit line voltage of the memory cell needs to be compared with three reference voltages to determine the data stored in the memory cell, according to an embodiment of the present invention, as shown in fig. 5, three comparators 501, 502, 503 may be provided to compare the potential of the memory cell with the three reference voltages at the same time to obtain the data stored in the memory cell, which may result in a faster reading speed, but the chip area occupied by the three comparators 501, 502, 503 may be larger.
Referring to FIG. 6, a voltage selection circuit and a voltage comparator 600 are provided for performing comparison in successive approximation according to another embodiment of the present invention, the data stored in the ferroelectric memory cell of the present invention is 2-bit data, which is denoted by D1D0, and when reading, first, the bit line voltage VB L of the ferroelectric memory cell to be read by the comparison circuit, i.e. the voltage comparator 600, and the second reference voltage VREF at the middle value2The comparison is made to obtain a first comparison result, and the first comparison result is taken as the most significant bit D1 of the 2-bit read result.
Then, if the bit line voltage VB L of the ferroelectric memory cell is higher than the second reference voltage, and the first comparison result is 1, the bit line voltage VB L and the third reference voltage VREF higher than the second reference voltage VREF2 are compared by the comparison circuit, i.e. the voltage comparator 6003Comparing to obtain a second comparison result, and regarding the second comparison result as the least significant bit D0. of the 2-bit read result if the ferroelectric memory cell bit line voltage VB L is lower than the second reference voltage, then the first comparison result is 0, and then the bit line voltage VB L is compared by a comparison circuit, i.e., a voltage comparator 600, with a first reference voltage VREF lower than the second reference voltage VREF21The comparison to obtain a third comparison result, and the third comparison result is taken as the least significant bit L SB of the 2-bit read result.
The embodiment shown in fig. 6 will be further explained with reference to specific circuits and timing diagrams.
Referring to fig. 7A, a schematic diagram of the sensing circuit 700 according to the embodiment shown in fig. 6 is shown, the sensing circuit 700 according to an embodiment of the present invention includes a comparator clock signal control circuit 701 composed of a delay circuit DE L AY and a not gate, a voltage selection circuit MUX702, a comparator SA703 and a NAND gate NAND 704, wherein an input terminal of the delay circuit DE L AY is connected to a READ compare READY signal READY, an output terminal of the delay circuit is connected to input terminals of the not gate composed of READ _ N, READ _ D and CK2, and an output terminal of the not gate NOR is used as a clock signal input terminal of the comparator SA.
Three input ends of the MUX voltage selection circuit 702 are respectively connected with three reference voltages VREF1, VREF2 and VREF2, a control end of the voltage selection circuit is connected with CK1 and D1, an output end VREF _ SE L of the voltage selection circuit 702 is connected with one input end of a voltage comparator SA703, and the other input end of the voltage comparator 703 is connected with a bit line B L of the ferroelectric memory cell.
Fig. 7B is a schematic diagram of a control signal generating circuit 705 of the readout circuit according to the present invention. As shown in the figure, the readout circuit control signal generation circuit 705 includes two D flip-flops DFF, in which an input terminal of the first D flip-flop DFF1 is connected to VDD, a clock signal terminal is connected to a READ READY signal READY, a reset terminal RST is connected to an inversion signal READ _ N to start reading, an output terminal CK1 of the D flip-flop is used as an input terminal of the second D flip-flop DFF2, a clock signal terminal of the second D flip-flop DFF2 is connected to a READ READY signal READY, a reset terminal RST of the second D flip-flop DFF2 is connected to an inversion signal READ _ N to start reading, and an output terminal of the second D flip-flop is CK 2.
Referring to fig. 7C, the readout signal latch circuit 706 of the present invention includes a third D flip-flop DFF3 for latching D1 bits of the readout signal, and a fourth D flip-flop DFF4 for latching D0 bits of the readout signal. The output end OUT of the comparator is used as the input end of the latch, the reverse signal READ _ N for starting reading is connected with the reset ends of the two flip-flops, the output end CK1 of the first flip-flop is connected with the clock signal end of the DFF3, and the output end CK2 of the second flip-flop is connected with the clock signal end of the DFF 4.
The read operation of the present invention will be described with reference to the timing diagram of fig. 7D and the circuit diagrams shown in fig. 7A-7C, taking the stored data D1D0 as 10 as an example.
Referring to the timing diagram of FIG. 7D, when the READ _ N signal goes low, the READ operation starts, when CK1 and D1 are both reset to 0 by the previous operation, VREF _ SE L is selected as VREF2 by the voltage selection circuit, and VREF2 is used as an input signal of voltage comparator SA 703;
then the voltage of W L and P L connected with the ferroelectric memory cell is increased, the voltage of B L is different according to the difference of the information stored in the ferroelectric memory cell, at this time, the voltage of B L is increased to VB L according to the stored information, VB L is used as another input signal of the voltage comparator 703;
since the READ _ N signal is at low level 0, CK _ SA rises and SA starts to operate, and since VB L is greater than VREF2, the output OUT of the comparator SA703 is 1, OUT _ N is 0, and the NAND (NAND gate) detects that OUT _ N is low, which indicates that SA compares the result, and then the READY signal goes high.
As shown in fig. 7B, the READY signal is an input clock of the first flip-flop DFF1 and the second flip-flop DFF2DFF, and the first flip-flop DFF1 starts to take data. CK1 thus rises, at which time CK2 remains 0;
as shown in fig. 7C, the input terminal CK1 of the third flip-flop DFF3 transmits OUT to the output terminal D1 through DFF3, and D1 rises to 1, and the first comparison result comes OUT, and since the voltage of VB L is higher than VREF2, the data D1 stored in the ferroelectric memory cell is 1, please continue to refer to fig. 7A, since CK1 is the control terminal of the voltage selection circuit, and the voltage selection circuit selects VREF _ SE L as VREF3 when CK1 is 1;
after a certain delay, CK _ SA is pulled low through NOR (NOR gate), then SA is reset, OUT and OUTN are both changed to be high, and then READY is changed to be low;
after a certain delay after READY goes low, CK _ SA is pulled high again by NOR (NOR gate), SA operates again, and the second comparison is started.
At this time, VB L of the ferroelectric memory cell is compared with the third reference voltage VREF3, and since the ferroelectric memory cell stores 10, VB L has a smaller value than the third reference voltage VREF3, and the signal OUT output by the comparator is 0.
Referring to fig. 7B, at the end of the second comparison, the output terminal CK2 of the second flip-flop DFF2 becomes 1.
Referring to FIG. 7C, when CK2 goes high, a signal of OUT 0 is sent to D0, resulting in D0 data of 0. The data D1 read at this time is 1, D0 is 0, which represents that the data stored in the ferroelectric memory cell is 10, and the data can be output through a peripheral logic circuit (not shown);
READ _ N then goes high, resetting the DFF inside and the READ operation ends.
Fig. 8A to 8D show a circuit diagram of a write circuit 500 of a ferroelectric memory according to the present invention and a timing chart thereof.
Fig. 8A is a schematic structural diagram of a write driver circuit, fig. 8B is a schematic structural diagram of a driver circuit of a transistor of a bit line driver circuit in the write driver circuit, and fig. 8C is a power supply generation circuit of the bit line driver circuit transistor in the write driver circuit.
As shown in fig. 8A, the write driver circuit 800 includes a bit line driver circuit connected to a bit line B L, the bit line driver circuit including first, second, third, and fourth transistors, wherein the gate of the first transistor PM1 is connected to the output terminal a of the first nand gate, one of the drain and the source thereof is connected to the first voltage VCC1, and the other of the drain and the source thereof is connected to the bit line of the ferroelectric memory cell to be written, the gate of the second transistor PM2 is connected to the output terminal B of the second nand gate, one of the drain and the source thereof is connected to the second voltage VCC2, and the other of the drain and the source thereof is connected to the bit line of the ferroelectric memory cell to be written, the gate of the third transistor PM3 is connected to the output terminal of the third nand gate, one of the drain and the source thereof is connected to the third voltage, and the other of the drain and the source thereof is connected to the bit line of the ferroelectric memory cell to be written, the gate of the fourth transistor PM4 is connected to the output terminal of the nand gate thereof, one of the drain and the source thereof is connected to the fourth voltage.
The write driver circuit further comprises a plate line driver circuit 802 connected to a plate line P L connected to one plate of the ferroelectric capacitor, the plate line driver circuit 802 comprising a fifth transistor PM5 and a sixth transistor NM6, wherein gates of the fifth transistor PM5 and the sixth transistor NM6 are connected to a plate line input voltage P L _ IN, a source of the fifth transistor is connected to a second voltage VCC2, a drain of the fifth transistor is connected to a plate line P L, a source of the sixth transistor NM6 is grounded, and a drain of the sixth transistor is connected to a plate line P L.
Fig. 8B shows a power supply generating circuit 803 of a bit line driving circuit transistor in the write driving circuit, where VCC1, VCC2, and VCC3 are internal voltage sources generated by VEXT (chip external voltage) through L DO (low dropout regulator), where VCC3 is VCC2-VCC 1.
Referring to fig. 8C, fig. 8C is a schematic diagram of a driving circuit of a transistor of a bit line driving circuit in a write driving circuit, wherein the bit line driving circuit 804 includes a first, a second, a third and a fourth and gates, two input terminals of the first and gate respectively input a most significant bit and a least significant bit of a signal to be written, an output terminal thereof is connected to one of input terminals of the first nand gate, input terminals of the second and gate respectively input the most significant bit and the least significant bit of the signal to be written, an output terminal thereof is connected to one of input terminals of the second nand gate, input terminals of the third and gate respectively input a most significant bit and a least significant bit of the signal to be written, an output terminal thereof is connected to one of input terminals of the third nand gate, and an input terminal of the fourth and gate respectively input a most significant bit and a least significant bit of the signal to be written, the output end of the first NAND gate is connected to one of the input ends of the fourth NAND gate; a second, a third and a fourth nand gate, wherein the other of the input ends of the first, the second, the third and the fourth nand gate inputs the write enable signal respectively; as shown in fig. 8A, the output a of the first nand gate is connected to the gate of the first transistor PM1, the output B of the second nand gate is connected to the gate of the second transistor PM2, the output C of the third nand gate is connected to the gate of the third transistor PM3, and the output D of the fourth nand gate is connected to the gate of the fourth transistor PM 4.
Fig. 8D shows a timing diagram of the write circuit 500.
Referring to fig. 8A to 8D, the writing method of the memory cell of the ferroelectric memory according to the present invention is as follows:
when writing 00, after the input D1D0 of the peripheral logic circuit (not shown) rises up to 00. W L, P L rises to VCC 2. after the WRITE enable signal WRITE (not shown) rises, A, B, C, D voltage rises, B L voltage is pulled down to 0. at this time, the voltage across the FRAM capacitor is VCC2, then P L voltage becomes 0, FRAM capacitor voltage also decreases to 0. as can be seen from fig. 3, the capacitor state is (Pr, 00);
when writing 01, after the peripheral logic circuit input D1D0 is 01. W L rises, P L rises to VCC 2. after the write signal rises, the A, B voltage rises, the C, D voltage goes low, and the B L voltage is pulled to VCC3, at which time the voltage across the FRAM capacitor is VCC1, then the P L, B L voltages go low to 0, and the FRAM capacitor voltage also goes low to 0, at which time the capacitor state is (Pr/3,01) as can be seen from fig. 3;
in writing 10, after the peripheral logic circuit input D1D0 is increased 10. W L, P L is increased to VCC 2. after the write signal is increased, the B, C voltage is increased, the A, D voltage is decreased, the B L voltage is pulled to VCC 1. then the P L voltage is decreased to 0 first, at which point the FRAM capacitor voltage is-VCC 1, then the B L voltage is decreased to 0, the FRAM capacitor voltage also becomes 0. as can be seen in fig. 3, at which point the capacitor state is (-Pr/3, 10);
when writing 11, the peripheral logic circuit input D1D0 rises 11. W L, P L rises to VCC 2. the write signal rises, the A, C voltage rises, the B, D voltage goes low, the B L voltage is pulled to VCC 2. then the P L voltage goes low to 0 first, at which point the FRAM capacitor voltage is-VCC 2, then the B L voltage goes to 0, the FRAM capacitor voltage also goes to 0, as can be seen in fig. 3, at which point the capacitor state is (Pr/3, 11).
Although some embodiments of the present invention have been described herein, those skilled in the art will appreciate that they have been presented by way of example only. Numerous variations, substitutions and modifications will occur to those skilled in the art in light of the teachings of the present invention without departing from the scope thereof. It is intended that the following claims define the scope of the invention and that methods and structures within the scope of these claims and their equivalents be covered thereby.
Claims (12)
1. A ferroelectric memory comprising:
a plurality of ferroelectric memory cells, each ferroelectric memory cell comprising a ferroelectric capacitor comprising an upper plate and a lower plate and a ferroelectric material between the upper plate and the lower plate;
a write circuit configured to apply a first voltage and a second voltage to two plates of a ferroelectric capacitor of a ferroelectric memory cell in forward and reverse directions, respectively, so that the ferroelectric material has corresponding first, second, third and fourth remnant polarization values, respectively, to write different stored data, wherein the different remnant polarization values correspond to the different stored data; and
and the reading circuit comprises a reference voltage generating circuit and a voltage comparison circuit, wherein the voltage comparison circuit can compare the acquired voltage at one end of the ferroelectric capacitor of the ferroelectric memory cell with the reference voltage generated by the reference voltage generating circuit to output different comparison results so as to read different storage data.
2. The ferroelectric memory of claim 1, wherein a value of the third remnant polarization and the fourth remnant polarization corresponding to the second voltage applied to the ferroelectric capacitor by the write circuit is 1/3 times a value of the first remnant polarization and the second remnant polarization corresponding to the first voltage applied to the ferroelectric capacitor by the write circuit.
3. The ferroelectric memory of claim 1, wherein the write circuit comprises first, second, third, and fourth AND gates, wherein the two input terminals of the first and gate input the inverted values of the most significant bit and the least significant bit of the signal to be written, the output end of the first NAND gate is connected to one of the input ends of the first NAND gate, the input ends of the second AND gate are respectively input with the most significant bit and the least significant bit of the signal to be written, the output end of the third AND gate is connected to one of the input ends of the second NAND gate, the input ends of the third AND gate are respectively input with the inverted value of the most significant bit and the least significant bit of the signal to be written, the output end of the fourth AND gate is connected to one of the input ends of the third NAND gate, the input ends of the fourth AND gate are respectively input with the inverted value of the most significant bit and the inverted value of the least significant bit of the signal to be written, and the output end of the fourth AND gate is connected to one of the input ends of the fourth NAND gate;
the first NAND gate, the second NAND gate, the third NAND gate and the fourth NAND gate, wherein the other input end of the first NAND gate, the second NAND gate, the third NAND gate and the fourth NAND gate respectively inputs a write enable signal; and
a first transistor, a second transistor, a third transistor and a fourth transistor, wherein the grid of the first transistor is connected with the output end of the first NAND gate, one of a drain and a source thereof is connected to a first voltage, and the other of the drain and the source thereof is connected to a bit line of the ferroelectric memory cell to be written, a gate of the second transistor is connected to an output terminal of the second nand gate, one of a drain and a source thereof is connected to a second voltage, and the other of the drain and the source thereof is connected to a bit line of the ferroelectric memory cell to be written, a gate of the third transistor is connected to an output terminal of the third nand gate, one of a drain and a source thereof is connected to a third voltage, and the other of the drain and the source thereof is connected to a bit line of the ferroelectric memory cell to be written, a gate of the fourth transistor is connected to an output terminal of the fourth nand gate, one of a drain and a source thereof is connected to a fourth voltage, and the other of the drain and the source thereof is connected to a bit line of the ferroelectric memory cell to be written.
4. The ferroelectric memory of claim 1, wherein the read circuit comprises:
four reference cells configured to generate first, second, third and fourth bit line voltages on bit lines thereof corresponding to 00, 01, 10, 11, respectively, in case of being written to one of 00, 01, 10, 11, respectively, wherein the first, second, third and fourth bit line voltages are sequentially raised;
a first reference voltage generating circuit for generating a first reference voltage according to the first and second bit line voltages, wherein the magnitude of the first reference voltage is between the magnitudes of the first and second bit line voltages;
the second reference voltage generating circuit generates a second reference voltage according to the second bit line voltage and the third bit line voltage, wherein the magnitude of the second reference voltage is between the magnitude of the second bit line voltage and the magnitude of the third bit line voltage; and
the third reference voltage generation circuit generates a third reference voltage according to the third and fourth bit line voltages, wherein the magnitude of the third reference voltage is between the magnitudes of the third and fourth bit line voltages.
5. The ferroelectric memory of claim 4, wherein the first reference voltage is an average of a sum of the first bit line voltage and the second bit line voltage, the second reference voltage is an average of a sum of the second bit line voltage and the third bit line voltage, and the third reference voltage is an average of a sum of the third bit line voltage and the fourth bit line voltage.
6. The ferroelectric memory of claim 4, wherein the voltage comparison circuit comprises three voltage comparators, wherein a first voltage comparator has one input terminal connected to the first reference voltage and another input terminal connected to the bit line of the ferroelectric memory cell; one input end of the second voltage comparator is connected with a second reference voltage, and the other input end of the second voltage comparator is connected with a bit line of the ferroelectric memory unit; one input end of the third voltage comparator is connected with a third reference voltage, and the other input end of the third voltage comparator is connected with a bit line of the ferroelectric memory unit.
7. The ferroelectric memory according to claim 4, wherein the voltage comparison circuit includes a voltage selection circuit and a voltage comparator, wherein three input terminals of the voltage selection circuit input one of the three reference voltages output by the reference voltage generation circuit, respectively, and an output terminal thereof is connected to one input terminal of the voltage comparator,
the other input end of the voltage comparator is connected with the bit line of the ferroelectric memory unit, and the output end of the voltage comparator outputs a comparison result;
the voltage comparison circuit also comprises a voltage comparator clock signal control circuit which comprises a delay circuit and a NOT gate, wherein the input end of the delay circuit is connected with the output end of the voltage comparator, and the output end of the NOT gate is connected with the clock signal input end of the voltage comparator.
8. The ferroelectric memory of claim 7, wherein the output of the voltage comparator comprises a first output and a second output, the first output and the second output outputting a comparison ready signal through a nand gate; the reading circuit further comprises a control signal generating circuit, wherein the control signal generating circuit comprises a shift register formed by two D triggers which are connected with each other, the output end of the first D trigger is connected with the control signal input end of the voltage selection circuit, and the output end of the second D trigger is connected with the input end of the clock signal control circuit of the voltage comparator.
9. The ferroelectric memory of claim 8, wherein the read circuit further comprises a sense signal latch circuit comprising a third D flip-flop for latching a most significant bit of the read signal, a fourth D flip-flop for latching a least significant bit of the read signal; the output end of the voltage comparator is connected with the input ends of the third D trigger and the fourth D trigger, the reverse signal for starting reading is connected with the reset ends of the third D trigger and the fourth D trigger, the output end of the first D trigger is connected with the clock signal end of the third D trigger, and the output end of the second D trigger is connected with the clock signal end of the fourth D trigger.
10. A method of performing a write operation to a ferroelectric memory as claimed in any one of claims 1 to 9, the method comprising
And applying a first voltage and a second voltage to two polar plates of a ferroelectric capacitor of the ferroelectric memory unit respectively in a forward direction and a reverse direction by using the write-in circuit, so that the ferroelectric material respectively has corresponding first, second, third and fourth remnant polarization values, and different storage data respectively corresponding to different remnant polarization values is written in.
11. A method of performing a read operation of the ferroelectric memory of any one of claims 1-7, the method comprising:
three reference voltages are generated with the read circuit,
and comparing the bit line voltage of the ferroelectric memory cell acquired by the reading circuit with the three reference voltages respectively, and reading data stored in the ferroelectric memory cell according to the comparison result.
12. A method of performing a read operation of the ferroelectric memory of any one of claims 1-6 and 8-9, the method comprising:
generating three reference voltages by using the reading circuit, wherein the third reference voltage is greater than the second reference voltage, and the second reference voltage is greater than the first reference voltage;
comparing a bit line voltage of a ferroelectric memory cell to be read with a second reference voltage to obtain a first comparison result, and taking the first comparison result as a most significant bit of the read result; and
if the first comparison result is that the bit line voltage of the ferroelectric memory cell is greater than the second reference voltage, the bit line voltage is compared with a third reference voltage to obtain a second comparison result and the second comparison result is taken as the least significant bit of the read result, and if the first comparison result is that the bit line voltage of the ferroelectric memory cell is less than the second reference voltage, the bit line voltage is compared with the first reference voltage to obtain a third comparison result and the third comparison result is taken as the least significant bit of the read result.
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| CN111833934A (en) * | 2020-07-30 | 2020-10-27 | 无锡拍字节科技有限公司 | Storage and calculation integrated ferroelectric memory and operation method thereof |
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| CN111833934A (en) * | 2020-07-30 | 2020-10-27 | 无锡拍字节科技有限公司 | Storage and calculation integrated ferroelectric memory and operation method thereof |
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