CN112562777A - Measuring circuit and method for ferroelectric memory capacitance - Google Patents
Measuring circuit and method for ferroelectric memory capacitance Download PDFInfo
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- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 description 1
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Abstract
The invention discloses a measuring circuit of a ferroelectric memory capacitor, which is arranged on a chip and comprises a reference voltage generating circuit and a capacitor measuring circuit, wherein the reference voltage generating circuit acquires different reference voltages by serially connecting resistors between a voltage source and the ground, a pMOS is used as a circuit switch, the capacitor measuring circuit is a differential or integral circuit consisting of a capacitor to be measured, a resistor and a voltage comparator, and the capacitance value of the capacitor can be calculated by measuring the output of the voltage comparator through an off-chip oscilloscope on the premise that the resistance value is known.
Description
Technical Field
The present invention relates to ferroelectric memory technology, and more particularly, to a circuit and method for measuring capacitance of a ferroelectric memory.
Background
The ferroelectric accumulator FRAM realizes data storage by utilizing the ferroelectric effect of ferroelectric crystals, and the ferroelectric materials commonly used at present mainly comprise PZT (lead zirconate titanate PbZr)xTil-xO3) SBT (strontium bismuth tantalate Sr)1-yBi2+xTa2O9) And High-K ferroelectric materials, and the like. The polarization properties of the ferroelectric material have two stable states, taking the PZT material as an example, fig. 1a and 1b show two stable states of the PZT ferroelectric material, where the PZT polarization direction is positive when a positive electric field is applied and is denoted as state "0", and the PZT polarization direction is negative when a negative electric field is applied and is denoted as state "1".
FIG. 2 shows the hysteresis loop of a FRAM capacitor showing different polarities of the ferroelectric capacitor under different electric fields, wherein QrDegree of remanent polarization, QsRefers to the spontaneous polarization, and VcRefers to the coercive field. In the absence of electric field strength, ± QrRepresenting states "0" "1", the applied electric field must be greater than + -V to obtain both statescWhere "±" denotes the direction of the applied electric field. For ferroelectric capacitors, when the direction of the applied electric field flows from the bit line to the plate line, "1" may be considered to be written into FRAM, and when the direction of the applied electric field flows from the plate line to the bit line, "0" may be considered to be written into FRAM.
In order to understand the storage performance of the ferroelectric memory and perform better read/write control, it is sometimes necessary to measure parameters such as the polarization degree of the ferroelectric capacitor in the ferroelectric memory and the capacitance value of the ferroelectric capacitor. In the prior art, if a ferroelectric capacitor is required to be measured, complex equipment is generally required, the performance requirement of the measuring equipment is high, and the test cost is high.
Disclosure of Invention
To solve some or all of the problems in the prior art, an aspect of the present invention provides a measuring circuit for capacitance of a ferroelectric memory, the measuring circuit being integrated on a chip and including:
a reference voltage generating circuit for generating a reference voltage, comprising a first voltage output terminal and/or a second voltage output terminal, and:
the P-type metal-oxide semiconductor field effect transistor pMOS is provided with a first end connected with a voltage source and a second end connected with a first end of a first resistor, wherein the first end and the second end are respectively a source electrode or a drain electrode;
the second end of the first resistor is connected with the first end of the second resistor, and the second end of the first resistor is connected to the first voltage output end;
the second end of the second resistor is connected with the first end of the third resistor, and meanwhile, the second end of the second resistor is connected to the second voltage output end; and
a third resistor, a second end of which is grounded; and
the capacitance measuring circuit comprises a resistor and a voltage comparator, wherein the resistor, the voltage comparator and the capacitor to be measured form a differential circuit and/or an integral circuit, and the differential circuit and/or the integral circuit comprises:
in the differential circuit, a first end of the capacitor to be tested is connected to a first signal input end, a second end of the capacitor to be tested is connected to a second signal input end through a resistor, a non-inverting input end of the voltage comparator is connected to a second end of the capacitor to be tested, and an inverting input end of the voltage comparator is connected to a first voltage output end of the reference voltage generating circuit; and
in the integrating circuit, the first end of the capacitor to be tested is connected to the first signal input end through a resistor, the second end of the capacitor to be tested is connected to the second signal input end, the non-inverting input end of the voltage comparator is connected to the second voltage output end of the reference voltage generating circuit, and the inverting input end of the voltage comparator is connected to the first end of the capacitor to be tested.
Furthermore, the first resistor, the second resistor and the third resistor are formed by connecting a plurality of resistors in series, and the resistance values of the resistors are equal to those of the resistors in the capacitance measuring circuit.
Furthermore, the capacitor to be tested is obtained by connecting the ferroelectric capacitors in a plurality of ferroelectric memory units in parallel.
Further, the capacitor to be tested comprises a plurality of capacitors connected in parallel, and the capacitors are the same as the storage capacitors of the ferroelectric memory.
Further, the capacitance measuring circuit further comprises a switch connected in parallel with the resistor.
Further, the first signal input end and the second signal input end are connected to a serial peripheral interface SPI, and the serial peripheral interface is connected to the driving control signal.
Based on the measurement circuit, another aspect of the present invention provides a capacitance measurement method, including:
providing a voltage V for a reference voltage generating circuit through a voltage source, and connecting the grid of the pMOS with a voltage of 0V;
inputting a high level at a first signal input terminal and inputting a low level at a second signal input terminal;
measuring the pulse width of the voltage comparator output; and
and calculating the capacitance according to the pulse width.
Further, the method further comprises calculating an actual resistance value of the resistor R, including:
and measuring the current of the reference voltage generating circuit through an ammeter, and further calculating to obtain the actual resistance value of the resistor R.
Further, based on the measuring circuit, the invention also provides a writing method of the ferroelectric memory, which comprises the following steps:
closing the switch in the integrating circuit; and
providing an electric field for a ferroelectric memory capacitor to effect writing, comprising:
inputting a high level at the first signal input terminal and inputting a low level at the second signal input terminal, and writing '1' in the ferroelectric memory; or
A low level is input to the first signal input terminal and a high level is input to the second signal input terminal, and "0" is written in the ferroelectric memory.
The invention provides a measuring circuit and a method of a ferroelectric memory capacitor. The measuring circuit and the measuring method have the following beneficial effects:
1. the reference voltage generating circuit adopts a plurality of same resistors which are connected in series to a voltage source to obtain different reference voltages, and the resistors are the same as the resistors adopted in the capacitance measuring circuit, so that the current of the reference voltage generating circuit is measured through external equipment, the accurate resistance value of the resistors can be obtained, and the calculation precision of the capacitance value is improved;
2. in the circuit, 256 ferroelectric memory units are connected in parallel to serve as capacitors to be tested, so that the pulse width output by the voltage comparator can be measured by an oscilloscope;
3. the input signal is rapidly generated by performing and calculation through the serial peripheral interface and the driving control signal;
4. the capacitance is measured by adopting a differential or integral circuit, so that the time that the capacitance is in a high electric field is ensured to be as short as possible, and the capacitance value of the capacitance is prevented from changing because the capacitance is in the high electric field for a long time;
5. the circuit is integrated on a chip, has a simple structure, and can conveniently measure the capacitance value of any point or wafer;
6. the measuring circuit can realize the measurement of the capacitance and the write operation of the ferroelectric memory.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the present invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar reference numerals for clarity.
FIGS. 1a-1b show two steady state schematic diagrams of the ferroelectric material PZT;
FIG. 2 shows a ferroelectric hysteresis loop of a ferroelectric memory capacitor;
FIG. 3 shows a schematic diagram of a reference voltage generation circuit of one embodiment of the present invention;
FIG. 4a shows a schematic of a differentiating circuit of one embodiment of the present invention;
FIG. 4b shows a schematic diagram of an integration circuit of one embodiment of the present invention;
FIG. 5a shows a schematic of the output of the differentiating circuit of one embodiment of the present invention;
FIG. 5b shows a schematic of the output of the integration circuit according to one embodiment of the present invention;
FIG. 6a illustrates a schematic diagram of the operation of a ferroelectric memory write "1" in accordance with one embodiment of the present invention; and
fig. 6b shows an operation diagram of writing "0" in the ferroelectric memory according to an embodiment of the present invention.
Detailed Description
In the following description, the present invention is described with reference to examples. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention. Similarly, for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention is not limited to these specific details. Further, it should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
Reference in the specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
It should be noted that the embodiment of the present invention describes the process steps in a specific order, however, this is only for the purpose of illustrating the specific embodiment, and does not limit the sequence of the steps. Rather, in various embodiments of the present invention, the order of the steps may be adjusted according to process adjustments.
When writing to the ferroelectric memory, the applied electric field needs to be larger than the coercive field of the capacitance of the ferroelectric memory, so that it is necessary to measure the capacitance of the ferroelectric memory to better determine the magnitude of the electric field required for writing. The equipment required for directly measuring the capacitance of the ferroelectric memory is complex and has high requirements on the precision of the equipment, which makes the test costly. In view of this problem, the inventor has invented a capacitance measuring circuit originally disposed on a chip, and the following describes the solution of the present invention with reference to the accompanying drawings of the embodiment.
A measuring circuit of a ferroelectric memory capacitor is integrated on a chip and comprises a reference voltage generating circuit and a capacitor measuring circuit, wherein the reference voltage generating circuit is used for generating a reference voltage, and the reference voltage is input to the capacitor measuring circuit so as to realize the measurement of the capacitor.
FIG. 3 shows a schematic diagram of a reference voltage generation circuit according to an embodiment of the invention. As shown in fig. 3, the reference voltage generating circuit includes a plurality of resistors connected in series to a voltage source, and employs a P-type metal-oxide semiconductor field effect transistor pMOS as a switch. The first end and the second end of the pMOS are respectively a source electrode or a drain electrode, when the grid voltage of the pMOS is 0V, the pMOS is conducted, and when the grid electrode is in a high level, the pMOS is cut off. The voltage source may be any on-chip dc voltage source. The resistance value of the resistor is calculated and determined according to a reference voltage required by a capacitance measuring circuit, in one embodiment of the present invention, the voltage source output voltage is 3V, the current flowing through the reference voltage generating circuit is 30uA, the reference voltage required by the capacitance measuring circuit is 1.2V and/or 1.8V, and therefore, the reference voltage generating circuit includes a first resistor, a second resistor, and a third resistor, wherein the first resistor, the second resistor, and the third resistor are connected in series, a first end of the first resistor is connected to a second end of the pMOS, a second end of the third resistor is grounded, a connection point of the first resistor and the second resistor is connected to a first voltage output end to output a first reference voltage, a connection point of the second resistor and the third resistor is connected to a second voltage output end to output a first reference voltage, and the first resistor, the second resistor, the third resistor, and the third resistor are connected to a second voltage output end to output a first, The third resistor has a resistance of 40k Ω, 20k Ω and 40k Ω, respectively.
Fig. 4a and 4a show two different capacitance measuring circuits according to embodiments of the present invention, respectively, where fig. 4a shows a differentiating circuit and fig. 4b shows an integrating circuit. For a ferroelectric memory, if a strong electric field is loaded at two ends of a capacitor of the ferroelectric memory for a long time, the capacitance value of the capacitor changes, and in order to accurately measure the capacitor, the duration of loading the strong electric field on the capacitor is as short as possible, based on the fact that a resistor, a voltage comparator and the capacitor to be measured form a differential circuit and/or an integral circuit, the pulse width output by the voltage comparator is measured through an off-chip oscilloscope, and the capacitance value of the capacitor is finally calculated, wherein:
in the differential circuit, a first end of the capacitor to be tested is connected to a first signal input end, a second end of the capacitor to be tested is connected to a second signal input end through a resistor, a non-inverting input end of the voltage comparator is connected to a second end of the capacitor to be tested, and an inverting input end of the voltage comparator is connected to the first voltage output end. Fig. 5a shows a schematic diagram of an output waveform of a voltage comparator in a differential circuit, as shown in the figure, after a test mode is activated, a first signal input end keeps a high level input, an output of the voltage comparator forms a rising edge, under the action of the differential circuit, a voltage at a non-inverting input end of the voltage comparator is gradually reduced from Vcc and is finally lower than a first reference voltage, at this time, an output of the voltage comparator forms a falling edge to obtain a pulse comp, the pulse and the width thereof can be conveniently measured by using an off-chip oscilloscope, and then a capacitance value C of a capacitor to be measured can be obtained according to the following formula:
C＝tcr/R/ln(Vcc/(refcr)，
wherein, tcr is the width of the pulse comp cr, R is the resistance of the resistor, Vcc is the input voltage of the differentiating circuit and refcr is the first reference voltage; and
in the integrating circuit, the first end of the capacitor to be measured is connected to the first signal input end through a resistor, the second end of the capacitor to be measured is connected to the second signal input end, the non-inverting input end of the voltage comparator is connected to the second voltage output end, and the inverting input end of the voltage comparator is connected to the first end of the capacitor to be measured. Fig. 5b shows a schematic diagram of an output waveform of a voltage comparator in the integration circuit, as shown in the figure, after the test mode is activated, the first signal input end keeps high level input, the output of the voltage comparator forms a rising edge, the voltage at the inverting input end of the voltage comparator gradually rises from 0 under the action of the integration circuit and is finally higher than the second reference voltage, at this time, the output of the voltage comparator forms a falling edge to obtain a pulse comprc, the pulse and the width thereof can be conveniently measured by using an off-chip oscilloscope, and then the capacitance value C of the capacitor to be measured can be obtained according to the following formula:
C＝trc/R/ln[1/(1-refrc/Vcc)]，
where trc is the width of the pulse comprc, R is the resistance of the resistor, Vcc is the input voltage of the integrating circuit and refrc is the second reference voltage.
In an embodiment of the present invention, the first signal input end and the second signal input end are connected to a serial peripheral interface SPI, and when a test is required, a specified sequence is sent through the SPI to activate a test mode, where "mode _ capm _ in" and "mode _ capm _ plin" in the sequence are respectively and-operated with a driving control signal to obtain a first signal input capm _ in and a second signal input capm _ plin, and in the test mode, mode _ capm _ in is 1 and mode _ capm _ plin is 0, so that after the driving control, the first signal input capm _ in is 1 and the second signal input capm _ plin is 0 are obtained.
In order to calculate the capacitance value of the capacitor more accurately, it is necessary to obtain an accurate resistance value, and the resistance value is directly measured, which has a high requirement for equipment, and based on this, the inventor proposes the following resistance value measuring method: in the reference voltage generating circuit, resistors identical to the resistors in the capacitance measuring circuit are connected in series to obtain a first resistor, a second resistor and a third resistor, and in consideration of the measurement accuracy of the oscilloscope, the resistance value of the resistor R used in the differentiating circuit and/or the integrating circuit is about 10k Ω, so as to meet the requirement. After the pMOS is turned on, the current value Isup in the reference voltage generating circuit can be conveniently measured by an off-chip ammeter, and then the accurate resistance value of the resistor R can be calculated according to the current value and the output voltage Vrefs of the voltage source:
R＝Vrefs/Isup/10。
in addition, since the accuracy of the oscilloscope is usually 100ns, the capacitance value of the capacitor in the differentiating circuit and/or the integrating circuit should be about 10pF, and in order to achieve this capacitance value, in the actual measurement, a plurality of, for example, 256 memory cells of the ferroelectric memory need to be connected in parallel, or a plurality of, for example, 256 ferroelectric capacitors equal to the memory capacitors of the memory cells of the ferroelectric memory need to be additionally arranged on the chip to be connected in parallel and then connected to the capacitance measuring circuit.
Based on the measurement circuit, the measurement of the capacitance of the ferroelectric memory can be performed according to the following method:
firstly, providing a voltage Vrefs for a reference voltage generating circuit through a voltage source, and connecting a grid electrode of the pMOS with a 0V voltage to obtain a first reference voltage and a second reference voltage;
next, the enabling chip sends a specified sequence through the SPI, so that the first signal input terminal outputs a high level and the second signal input terminal outputs a low level;
next, measuring the pulse width output by the voltage comparator through an off-chip oscilloscope, and measuring the current Isup in the reference voltage generating circuit through an off-chip ammeter; and
and finally, calculating the capacitance value of the capacitor:
c ═ tcr/R/ln (Vcc/(refcr), or
C＝trc/R/ln[1/(1-refrc/Vcc)]，
Where, tcr is the width of the pulse output by the differentiating circuit, trc is the width of the pulse output by the integrating circuit, R ═ Vrefs/Isup/10 is the resistance of the resistor, Vcc is the input voltage of the differentiating circuit and/or the integrating circuit, refcr is the first reference voltage, and refrc is the second reference voltage.
The measuring circuit can also realize the write operation of the ferroelectric memory after being simply modified, if the function is to be realized, only one switch is connected in parallel at two ends of the resistor in the integrating or differentiating circuit, and the switch is closed during the write operation, so that pgm is 1.
The following describes the process of the write operation specifically by taking the integrating circuit as an example:
when "1" needs to be written, as shown in fig. 6a, the switch is first closed, and then a specified sequence is sent through the SPI, so that capm _ in is 1 and capm _ plin is 0, and at this time, the electric field flowing through the capacitor of the ferroelectric memory is a positive electric field, and writing of "1" is completed; and
when "0" needs to be written, as shown in fig. 6b, the switch is first closed, and then a specified sequence is sent through the SPI so that capm _ in becomes 0 and capm _ plin becomes 1, and at this time, the electric field flowing through the ferroelectric memory capacitor becomes a negative electric field, and writing of "0" is completed.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various combinations, modifications, and changes can be made thereto without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims (10)
1. A measurement circuit of ferroelectric memory capacitance, characterized in that, disposed on a chip, includes:
a reference voltage generation circuit configured to generate a reference voltage, the reference voltage generation circuit including a first voltage output terminal and/or a second voltage output terminal; and
the capacitance measuring circuit comprises a resistor and a voltage comparator, wherein the resistor, the voltage comparator and the capacitor to be measured form a differential circuit and/or an integral circuit, and the differential circuit and/or the integral circuit comprises:
in the differential circuit, a first end of the capacitor to be tested is connected to a first signal input end, a second end of the capacitor to be tested is connected to a second signal input end through a resistor, a non-inverting input end of the voltage comparator is connected to a second end of the capacitor to be tested, and an inverting input end of the voltage comparator is connected to a first voltage output end of the reference voltage generating circuit; and
in the integrating circuit, the first end of the capacitor to be tested is connected to the first signal input end through a resistor, the second end of the capacitor to be tested is connected to the second signal input end, the non-inverting input end of the voltage comparator is connected to the second voltage output end of the reference voltage generating circuit, and the inverting input end of the voltage comparator is connected to the first end of the capacitor to be tested.
2. The measurement circuit of claim 1, wherein the reference voltage generation circuit comprises:
the P-type metal-oxide semiconductor field effect transistor pMOS is provided with a first end connected with a voltage source and a second end connected with a first end of a first resistor, wherein the first end and the second end are respectively a source electrode or a drain electrode;
a second end of the first resistor is connected with a first end of the second resistor, and a second end of the first resistor is connected to the first voltage output end;
a second end of the second resistor is connected with a first end of the third resistor, and meanwhile, a second end of the second resistor is connected to the second voltage output end; and
and a second end of the third resistor is grounded.
3. The measurement circuit of claim 2, wherein the first resistor, the second resistor, and the third resistor are formed by serially connecting a plurality of identical resistors, and the resistors have the same resistance as the resistors in the capacitance measurement circuit.
4. The measurement circuit of claim 1, wherein the capacitor under test is formed by connecting a plurality of ferroelectric capacitors in parallel, the ferroelectric capacitors being identical to the storage capacitors of the ferroelectric memory.
5. The measurement circuit of claim 2, wherein the capacitance measurement circuit further comprises a switch connected in parallel with the resistor.
6. The measurement circuit of claim 1, wherein the first signal input and the second signal input are connected to a Serial Peripheral Interface (SPI), and the SPI is connected to a drive control signal.
7. A method of capacitance measurement based on a measurement circuit according to any of claims 2 to 6, comprising the steps of:
providing a voltage to a reference voltage generation circuit through a voltage source to generate a first reference voltage and/or a second reference voltage;
inputting a high level at a first signal input terminal and inputting a low level at a second signal input terminal;
measuring the pulse width of the voltage comparator output; and
and calculating the measured value of the capacitor to be measured according to the pulse width.
8. The method of claim 7, wherein: when a differential circuit is adopted, the measured value C of the capacitor to be measured is tcr/R/ln (Vcc/(refcr), wherein tcr is the pulse width output by the voltage comparator, R is the resistance value of the resistor, Vcc is the input voltage of the differential circuit and refcr is the first reference voltage output by the first voltage output end, and when an integral circuit is adopted, the measured value C of the capacitor to be measured is trc/R/ln [1/(1-refrc/Vcc) ], wherein trc is the pulse width output by the voltage comparator, R is the resistance value of the resistor, and Vcc is the input voltage of the integral circuit and refrc is the second reference voltage output by the second voltage output end.
9. The method of claim 8, further comprising calculating an actual resistance value of the resistor R, including:
and if the resistors forming the first resistor, the second resistor and the third resistor are the same as the resistors in the differential circuit and the integrating circuit, measuring the current of the reference voltage generating circuit through an ammeter, and further calculating to obtain the actual resistance value of the resistor.
10. A ferroelectric memory writing method based on the measuring circuit of claim 5, comprising the steps of:
closing the switch; and
providing an electric field for a ferroelectric memory capacitor to effect writing, comprising:
inputting a high level at the first signal input terminal and a low level at the second signal input terminal to write a "1" in the ferroelectric memory; or
A low level is input at the first signal input terminal and a high level is input at the second signal input terminal to write "0" in the ferroelectric memory.
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| JP2005322889A (en) * | 2004-04-05 | 2005-11-17 | Fujitsu Ltd | Measuring method of ferroelectric capacitor and designing method of ferroelectric memory |
| US20090001998A1 (en) * | 2006-02-07 | 2009-01-01 | Kiyoshi Tateishi | Capacitance Detecting Apparatus |
| CN111402939A (en) * | 2020-03-26 | 2020-07-10 | 珠海拍字节信息科技有限公司 | Ferroelectric memory and method of operating the same |
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