CN112712831A - Ferroelectric memory and operation method thereof - Google Patents
Ferroelectric memory and operation method thereof Download PDFInfo
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- CN112712831A CN112712831A CN202110043971.4A CN202110043971A CN112712831A CN 112712831 A CN112712831 A CN 112712831A CN 202110043971 A CN202110043971 A CN 202110043971A CN 112712831 A CN112712831 A CN 112712831A
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- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
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Abstract
The invention discloses a ferroelectric memory, which comprises a plurality of byte storage units and a first selection circuit. Each byte memory cell comprises a plurality of memory cells, each memory cell comprises a bit line and a plate line, and the plate lines of the byte memory cells are independent. The first selection circuit comprises a plurality of first selection sub-circuit modules, one end of each first selection sub-circuit module is electrically connected to the bit line of each memory unit of each byte memory unit, the other end of each first selection sub-circuit module is connected to a plurality of corresponding sensing circuits, the sensing circuits output sensing signals according to input signals of the bit lines of the connected memory units, and when the first selection sub-circuit module corresponding to any byte memory unit is switched on, the first selection sub-circuit modules corresponding to the rest byte memory units are switched off.
Description
Technical Field
The invention relates to the technical field of ferroelectric storage, in particular to a ferroelectric memory and an operation method thereof.
Background
In recent years, ferroelectric memories have received increasing attention as a new type of memory with high writing speed and high number of times of writing and reading. Ferroelectric memory is a special technology of non-volatile memory. When an electric field is applied to a ferroelectric transistor, the central atom stays in a first low energy state along the electric field, and when an electric field reversal is applied to the same ferroelectric transistor, the central atom moves in the crystal along the direction of the electric field and stays in a second low energy state. A large number of central atoms move in the crystal unit cell and are coupled to form ferroelectric domains, and the ferroelectric domains form polarization charges under the action of an electric field. The binary stable state of the ferroelectric material enables the ferroelectric to be used as a memory.
When the electric field is removed, the central atom is kept in a low energy state, and the state of the memory is also preserved and does not disappear, so that whether the memory cell is in a '1' state or a '0' state can be judged by high polarization charges formed by the ferroelectric domain in a reverse way under the electric field or low polarization charges formed by no reverse way. The inversion of the ferroelectric domain does not require a high electric field, but can change the state of "1" or "0" of the memory cell only with a general operating voltage; nor does it require a charge pump to generate high voltages for data erasure, and thus there is no erase delay. The characteristic enables the ferroelectric memory to continue to store data after power failure, and the ferroelectric memory has high writing speed, infinite writing life and difficult writing failure. Moreover, compared with the existing nonvolatile memory technology, the ferroelectric memory has higher writing speed and longer read-write life.
Reading of the ferroelectric memory as shown in fig. 1, when reading data stored in a ferroelectric cell, the data stored in the cell is determined by a potential difference between a bit line bl of the cell and a reference line. As shown in the figure, when reading the stored data of the corresponding cell, bl <0>, wl0, the voltage of wl0 is set to high level, so that the source/drain path of the transmission transistor connected to wl0 is turned on, which means that the storage node bl0 is directly connected to the bit line bl <0>, the corresponding reference point blref0 is connected to the reference line blref <0> according to the same principle, and at this time, the data stored in the cell can be judged by the potential difference between the bit line and the reference line. As for the storage node bl0, the equivalent circuit is as shown in fig. 2, a ferroelectric capacitor Ccell exists between the storage nodes bl0 and PL, the capacitance of the bit line bl <0> itself metal line is Cm, and since the bit line bl <0> is not only connected to the word line wl0 through the transfer transistor but also connected to the rest word line wl1 through the transfer transistor, etc., the potential of these word lines is 0 at this time, so there is a parasitic capacitance between the bit line bl <0> and this part of word lines, and since these capacitances are in parallel relationship, the equivalent is Σ Cgs in fig. 2, and thus, the capacitance Cbl of the storage node bl0 can be calculated as Cm + Σ Cgs _ i, i is 0, …, n-1, where n is the number of rows of word lines; the voltage Vbl of the storage node bl0 is Vpl × Ccell/(Ccell + Cbl), where Vbl is the bit line bl <0>, i.e. the voltage at the storage node bl0, and Vpl is the voltage on the plate line PL. Since the magnitude of the potential difference between the bit line and the reference line is usually measured directly, in practical applications, it is necessary to add a sensing circuit between the bit line and the reference line, which includes a sense amplifier and a corresponding circuit, to differentially amplify the small signals on the bit line and the reference line into the outputs of the recognizable standard logic values "1" and "0". As shown in fig. 3, half of the bit lines are used as reference lines in the conventional 2T2C ferroelectric memory structure, and thus one set of sensing circuits is required for each pair of bit lines, for example, 64 sets of sensing circuits are required if there are 128 bit lines, and as shown in fig. 4, a common reference line is provided in the 1T1C ferroelectric memory structure, and thus one set of sensing circuits is required for each bit line to be connected to the common reference line, for example, 128 sets of sensing circuits are required if there are 128 bit lines. As the capacity of the ferroelectric memory increases, the more sense amplifiers and sensing circuits are required, so that the volume of the ferroelectric memory is also increased by multiple times, which is contrary to the development requirement of miniaturization and high density of the ferroelectric memory.
Disclosure of Invention
To address some or all of the problems in the prior art, an aspect of the present invention provides a ferroelectric memory, including:
the memory comprises a plurality of byte memory units, a plurality of bit lines and a plurality of plate lines, wherein each byte memory unit comprises a plurality of memory units, each memory unit comprises a bit line and a plate line, and the plate lines of the byte memory units are mutually independent; and
a first selection circuit including a plurality of first selection sub-circuit blocks, each of the first selection sub-circuit blocks having one end electrically connected to a bit line of a respective memory cell of each of the byte memory cells and the other end connected to a plurality of corresponding sensing circuits, wherein,
the sensing circuit outputs a sensing signal according to an input signal of a bit line of the connected memory unit, when the first selection sub-circuit module connected with any byte memory unit is turned on, the first selection sub-circuit modules connected with the rest byte memory units are turned off, so that the bit line of only one byte memory unit is electrically connected to the sensing circuit at a time.
Furthermore, the sensing circuit includes a plurality of sense amplifiers, when a byte memory cell is selected, the first input terminal of each sense amplifier is electrically connected to the bit line of each memory cell of the byte memory cell through the first selection sub-circuit module in sequence, and the second input terminal is electrically connected to the reference line corresponding to the bit line through the first selection sub-circuit module or directly.
Further, the first selection sub-circuit module comprises a plurality of selection switches, one end of each selection switch is connected to one bit line, and the other end of each selection switch is connected to the sensing circuit.
Further, the selection switch includes:
an inverter having an input coupled to the selection signal generation circuit;
a first switching transistor having a gate coupled to the selection signal generation circuit; and
a second switching transistor having a gate coupled to an output of the inverter.
Further, the signal generation circuit includes:
a command decoder which encodes according to a memory control command to form a memory address;
and an address decoder communicably connected to the command decoder, the address decoder decoding the memory address to generate a selection signal.
Further, the ferroelectric memory further includes a plate line voltage generating circuit including:
a first transistor having a first terminal connected to an input voltage and a gate coupled to the first terminal;
a linear voltage stabilizing module, an input end of which is connected to the second end of the first transistor; and
and the voltage division module is connected in series with the second end of the first transistor and is connected to the ground wire, wherein the first end of the first transistor refers to the source electrode or the drain electrode of the first transistor.
Further, the linear voltage regulation module includes an operational amplifier, a positive input terminal of the operational amplifier is connected to the second terminal of the first transistor, and a negative input terminal of the operational amplifier is connected to the output terminal of the amplifier; and/or
The voltage division module comprises a second transistor or a resistor, wherein the first end of the second transistor or the resistor is connected to the second end of the first transistor, the second end of the second transistor or the resistor is grounded, and the grid electrode of the second transistor is coupled to the bias circuit, wherein the first end of the second transistor refers to the source electrode or the drain electrode of the first transistor.
Furthermore, the ferroelectric memory further comprises a plurality of sectors, wherein each sector comprises N byte memory cells, all bit lines in each sector are connected to the plurality of bit line coupling lines in a one-to-one correspondence manner through one second selection sub-circuit module, when the second selection sub-circuit module corresponding to any sector is turned on, the second selection sub-circuit modules corresponding to the rest sectors are turned off, and the sensing circuit is connected to the bit line coupling lines through the first selection sub-circuit module.
Further, the second selection sub-circuit module includes a plurality of the selection switches, and the bit lines are connected to bit line coupling lines through the selection switches in a one-to-one correspondence.
Another aspect of the present invention provides an operating method of the ferroelectric memory, including:
according to the selection signal, controlling the corresponding second selection sub-circuit module to be switched on, enabling the rest second selection sub-circuit modules to be switched off, and selecting a bit line of a storage unit of one sector to be connected to the bit line coupling line; and
and controlling the corresponding first selection sub-circuit module to be switched on according to the selection signal, switching off the other first selection sub-circuit modules, and selecting a bit line coupling line of one byte storage unit to be connected to the sensing circuit to read and write the byte at the designated position.
The invention provides a ferroelectric memory, which is characterized in that a first selection circuit is added in the ferroelectric memory, so that each byte memory cell in the ferroelectric memory shares one group of sensing circuits, specifically, the same bit of each byte shares one sense amplifier. In order to realize the function, each byte memory cell comprises an independent plate line, and in order to ensure the correctness of reading and writing, the invention also provides a plate line voltage generating circuit, so that the plate line voltage is at least Vt less than the power supply voltage. Therefore, compared with the existing ferroelectric memory, the ferroelectric memory provided by the invention not only reduces the complexity of the circuit, but also saves a large amount of wiring space, so that the size of the ferroelectric memory is optimized, and the storage with larger capacity can be realized on a smaller size.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the present invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar reference numerals for clarity.
FIG. 1 shows a read schematic of a ferroelectric memory of the prior art;
FIG. 2 is a schematic diagram showing an equivalent circuit at the time of reading of a ferroelectric memory in the prior art;
FIG. 3 shows a schematic diagram of a sensing circuit of a prior art 2T2C architecture memory;
FIG. 4 shows a schematic diagram of a sensing circuit of a prior art 1T1C architecture memory;
FIG. 5 is a schematic diagram of a 2T2C ferroelectric memory according to an embodiment of the present invention;
FIG. 6 is a schematic sector view of a 2T2C architecture ferroelectric memory in accordance with one embodiment of the present invention;
FIG. 7 is a partial structural schematic diagram of a 2T2C structural ferroelectric memory in accordance with one embodiment of the present invention;
FIG. 8 is a schematic structural diagram of a 1T1C ferroelectric memory according to an embodiment of the present invention;
FIG. 9 is a schematic diagram showing the structure of a selection switch of a ferroelectric memory according to an embodiment of the present invention; and
fig. 10 is a schematic diagram illustrating a plate line voltage generating circuit of a ferroelectric memory according to an embodiment of the present invention.
Detailed Description
In the following description, the present invention is described with reference to examples. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention. Similarly, for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention is not limited to these specific details. Further, it should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
Reference in the specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
It should be noted that the embodiment of the present invention describes the process steps in a specific order, however, this is only for the purpose of illustrating the specific embodiment, and does not limit the sequence of the steps. Rather, in various embodiments of the present invention, the order of the steps may be adjusted according to process adjustments.
The invention provides a ferroelectric memory, which greatly reduces the wiring space by sharing a sensing circuit, aiming at the problem that the storage density is difficult to improve because the wiring space required by the sensing circuit in the prior art is large. The solution of the invention is further described below with reference to the accompanying drawings of embodiments.
Fig. 5 shows a schematic structural diagram of a ferroelectric memory with a 2T2C structure according to an embodiment of the present invention.
As shown in fig. 5, the ferroelectric memory with 2T2C structure includes a plurality of byte memory cells, each byte memory cell includes 8 memory cells, each memory cell includes a pair of bit lines and plate lines, and the plate lines of the respective byte memory cells are independent of each other. As shown in the figure, each ferroelectric unit in each byte memory unit bytek is connected with the plate line PL < k > corresponding to the byte memory unit, blk <8>: blk <15> is respectively corresponding to blk <0>: blk <7> in a one-to-one manner, so as to realize the reading and writing of 0-7 bits of each byte, each bit line is connected to a sensitive amplifier in a sensing circuit through a first selection circuit, the first selection circuit comprises a plurality of first selection sub-circuit modules, each first selection sub-circuit module is corresponding to the byte memory unit bytek in a one-to-one manner, and one first selection sub-circuit module is electrically connected with the bit line of each memory unit in one byte memory unit bytek. In the embodiment of the present invention, bit lines of memory cells in the same location of each byte memory cell are respectively connected to the same sense amplifier through the first selection sub-circuit modules corresponding to each byte memory cell, for example, bl0<0>, bl1<0>, … bl7<0> … of each byte memory cell, respectively connected to the positive input terminal of the first sense amplifier sa <0> through the first selection sub-circuit modules corresponding to each byte memory cell, bl0<8>, bl1<8>, … bl7<8> …, respectively connected to the negative input terminal of the first sense amplifier sa <0> through the first selection sub-circuit modules corresponding to each byte memory cell, and so on, until bl0<7>, bl1<7>, … bl7<7> …, respectively connected to the positive input terminal of the eighth sense amplifier sa <7> through the first selection sub-circuit modules corresponding to each byte memory cell, bl0<15>, bl1<15>, and … bl7<15> … are respectively connected to the negative input terminal of the eighth sense amplifier sa <7> through the first selection sub-circuit block corresponding to each byte memory cell. When any one of the first selection sub-circuit modules is turned on, the rest of the first selection sub-circuit modules are turned off, so that only one bit line of one byte memory cell is connected to the sensing circuit at a time, and further sharing of the sensing circuit is realized, so that only 8 groups of sensing circuits are needed in the whole ferroelectric memory, and if the ferroelectric memory comprises 128 bit lines, compared with the prior art, the number of the sensing circuits is reduced from 64 groups to 8 groups, so that the wiring space is greatly reduced, and the storage density is improved.
In one embodiment of the invention, the first selection sub-circuit block comprises a plurality of selection switches YAswitch, and all yaswitches in the same first selection sub-circuit block are closed or opened at the same time. Each of the selection switches YA switch is connected to the bit lines of the memory cells in each byte memory cell in a one-to-one correspondence, and for the configuration shown in fig. 5, each of the first selection sub-circuit blocks includes 16 selection switches YA switch, which are connected to 16 bit lines in one byte memory cell, respectively.
Fig. 9 is a schematic diagram showing a structure of a selection switch of a ferroelectric memory according to an embodiment of the present invention. As shown in fig. 9, the selection switch YA switch includes a first switching transistor M1, a second switching transistor M2, and an inverter F1, wherein: the input end of the inverter F1 is coupled to a selection signal generating circuit; the first switch transistor M1 has a source-drain path and a gate, the source-drain path of the first switch transistor M1 is connected between the bit line bl and the sensing circuit, and the gate of the first switch transistor M1 is coupled to the selection signal generating circuit; the second switch transistor M2 has a source-drain path and a gate, the source-drain path of the second switch transistor M2 is connected between the bit line bl and the sensing circuit, and the gate of the second switch transistor M2 is coupled to the output terminal of the inverter F1. When a byte memory cell is selected, the selection signal connected to the byte memory cell is at a high level, and both the first switching transistor and the second switching transistor are turned on. The second switching transistor M2 is used as a redundant transistor of the first switching transistor M1, and redundant conduction is realized when the first switching transistor is damaged, so that the operation of the memory cell is not influenced. The selection signal generation circuit is used for determining a storage address according to a storage control instruction, and comprises a command decoder and an address decoder, wherein the command decoder encodes according to the storage control instruction to form a storage address and sends the storage address to the address decoder, and the address decoder decodes the storage address to generate a selection signal after receiving the storage address.
In one embodiment of the present invention, in order to avoid the limitation of the number of bit lines connected to word lines, the ferroelectric memory is further divided into a plurality of sectors. Fig. 6 shows a sector schematic diagram of a 2T2C structure ferroelectric memory according to an embodiment of the present invention. As shown in fig. 6, a 2T2C ferroelectric memory includes a plurality of sectors (sectors), each of which includes 128 word lines WL and a plurality of byte memory cells, each of which includes 16 bit lines bl and 1 plate line, the bit lines being coupled to bit line coupling lines sabl through a second selection circuit. In an embodiment of the present invention, the second selection circuit includes a plurality of second selection sub-circuit modules, and the second selection sub-circuit modules include a plurality of selector switches, the number of the selector switches is consistent with the number of bit lines included in a sector, when the second selection sub-circuit module corresponding to any sector is turned on, all the selector switches included in the second selection sub-circuit module are turned on, and the second selection sub-circuit modules corresponding to the remaining sectors are turned off. The selector switch is the same as the YA switch in structure, and can also be seen in fig. 9, which includes a first switch transistor, a second switch transistor and an inverter, where: the input end of the inverter is coupled to the selection signal generating circuit; the first switch transistor is provided with a source-drain path and a grid electrode, the source-drain path of the first switch transistor is connected between the bit line and the bit line coupling line, and the grid electrode of the first switch transistor is coupled to the selection signal generating circuit; the second switch transistor is provided with a source-drain path and a grid electrode, the source-drain path of the second switch transistor is connected between the bit line and the bit line coupling line, and the grid electrode of the second switch transistor is coupled to the output end of the phase inverter. When a sector is selected, the selection signal connected to the sector is at a high level, and the first switching transistor and the second switching transistor are both turned on. The second switch transistor is used as a redundant transistor of the first switch transistor, and redundant conduction is realized when the first switch transistor is damaged, so that the operation of the memory unit is not influenced.
To more clearly describe the scheme of the present invention, fig. 7 shows a schematic partial structure diagram of a 2T2C structure ferroelectric memory according to an embodiment of the present invention. The byte memory unit bytek comprises a plurality of memory units which are arranged in a matrix structure of i rows and j columns, wherein each memory unit is connected with a plate line PL < k > corresponding to the byte memory unit, the memory unit of the ith row is connected with a word line wl < i > corresponding to the ith row, and the memory unit of the jth column is connected with a bit line bl < j > corresponding to the jth column. In one embodiment of the invention, the byte memory cells bytek comprise 128 rows and 16 columns of memory cells. Wherein the memory cell includes a ferroelectric capacitor and a transistor, wherein the ferroelectric capacitor has a first plate and a second plate, the first plate is connected to a plate line, each byte memory cell has a separate plate line, as shown in fig. 8, sector <0> -PL <0> -bl <0> tobl <15> refers to the plate line PL <0> of the first byte memory cell byte0 in the first sector <0>, wherein bl <0> to bl <15> of the byte memory cell are connected to the plate line PL <0>, sector <1> -PL <0> -bl <0> tobl <15> refers to the plate line PL <0> of the first byte memory cell byte0 in the second sector <1>, wherein bl <0> to bl <15> of the byte memory cell are connected to the plate line PL <0>, and so on; and the source-drain path of the transistor is connected between the second polar plate and the bit line corresponding to the row, and the grid electrode is coupled to the word line corresponding to the row. As shown in FIG. 8, each bit line is connected to a bit line coupling line through a sector switch, specifically, a bit line bl <0> is connected to a bit line coupling line table <0> through a sector switch, the bit line coupling line table <0> is connected to a positive input terminal of a first sense amplifier table <0> through a selector switch YA switch, a bit line bl <1> is connected to a bit line coupling line table <1> through a sector switch, the bit line coupling line table <1> is connected to a positive input terminal of a second sense amplifier table <1> through a selector switch YA switch, and so on until the bit line bl <7> is connected to the bit line coupling line table <7> through a sector switch, the bit line coupling line table <7> is connected to a positive input terminal of an eighth sense amplifier table <7> through a selector switch YA switch, and the bit line bl <8> is connected to the bit line coupling line <8> through a sector switch, the bit line coupling line bl <8> is connected to a negative input terminal of the first sense amplifier table <0> through a selector switch And the bit line bl <9> is connected to a bit line coupling line sable <9> through a sector switch, the bit line coupling line sable <9> is connected to a negative input end of a second sense amplifier salat <1> through a selector switch YA switch, and so on until the bit line bl <15> is connected to the bit line coupling line sable <15> through a sector switch, the bit line coupling line sable <15> is connected to a negative input end of an eighth sense amplifier salat <7> through a selector switch YAswitch, and in addition, the positive and negative input ends of each sense amplifier are connected with a write-in circuit write/write-back to realize the write-in and write-back of data.
Fig. 8 shows a schematic structural diagram of a ferroelectric memory with a 1T1C structure according to an embodiment of the present invention. It is similar to the ferroelectric memory structure of 2T2C structure, except that in the ferroelectric memory of 1T1C structure, the number of bit lines of each memory cell is 1, each memory cell of each byte memory cell bytek is connected to the plate line PL < k > corresponding to the memory cell of this byte, the bit line bl <0> is connected to the positive input terminal of the first sense amplifier salat <0> through YAswitch, the bit line bl <1> is connected to the positive input terminal of the second sense amplifier salat <1> through YAswitch, and so on, until the bit line bl <7> is connected to the positive input terminal of the eighth sense amplifier salat <7> through YAswitch, the negative input terminal of each sense amplifier is connected to the reference voltage line, it can be seen that the sense circuits are shared by matching YAswitch, so that only 8 sets of sense circuits are needed in the whole ferroelectric memory, if the ferroelectric memory includes 128 bit lines, compared with the prior art, the number of the sensing circuits is reduced from 128 groups to 8 groups, the wiring space is greatly reduced, and the storage density is improved. Likewise, the ferroelectric memory may also be divided into a plurality of sectors by a second selection circuit.
In the embodiment of the invention, since each byte memory cell shares the sensing circuit, only one byte memory cell is connected with the sensing circuit at a time to realize read-write operation, so that each byte memory cell needs an independent plate line and a corresponding plate line voltage generating circuit.
The reading and writing of the ferroelectric memory are realized by forming electric fields in different directions on the ferroelectric capacitance mainly through the cooperation of the bit lines and the plate lines. To avoid the voltage at the other end of the ferroelectric capacitor being lower than Vpl when Vpl is high, thereby creating an electric field that is inconsistent with the requirements, it is often necessary to pull the word line voltage high by at least one Vt. However, if a higher voltage is required, the required circuit is complex, a series of components such as a charge pump or booster, a bandgap reference voltage source (bandgap) and a low dropout regulator (LDO) are required, and a large amount of power is consumed. To address this problem, in one embodiment of the present invention, a plate line voltage generating circuit generates a PL voltage Vpl smaller than the supply voltage Vcc to ensure the direction of the electric field and thus the correctness of reading and writing. Fig. 10 is a schematic diagram illustrating a plate line voltage generating circuit of a ferroelectric memory according to an embodiment of the present invention. As shown in fig. 10, the plate-line voltage generating circuit includes a first transistor M3, a low dropout linear regulator module, and a voltage divider module, wherein a first terminal of the first transistor M3 is connected to a power supply voltage Vcc, a gate thereof is coupled to the first terminal, and an input terminal of the linear regulator module is connected to a second terminal of the first transistor; the voltage dividing module is connected in series to the second terminal of the first transistor and grounded, wherein the first terminal of the first transistor M3 refers to the source or the drain of the first transistor. In an embodiment of the present invention, the linear regulator module includes an operational amplifier OP, a positive input terminal of the operational amplifier OP is connected to the second terminal of the first transistor M3, and a negative input terminal of the operational amplifier OP is connected to the output terminal of the operational amplifier OP. In an embodiment of the invention, the voltage dividing module includes a second transistor M4, a first terminal of the second transistor M4 is connected to a second terminal of the first transistor, the second terminal is grounded, and a gate is coupled to the bias circuit nbias, wherein the first terminal of the second transistor M4 refers to a source or a drain of the second transistor. It should be understood that, in other embodiments of the present invention, the voltage dividing module may also include a resistor, a first terminal of the resistor is connected to the second terminal of the first transistor, and a second terminal of the resistor is grounded. The linear regulator module may also employ other LDO devices or circuits.
The invention provides a ferroelectric memory, which is characterized in that a first selection circuit is added in the ferroelectric memory, so that each byte memory cell in the ferroelectric memory shares one group of sensing circuits, specifically, the same bit of each byte shares one sense amplifier. In order to realize the function, each byte memory cell comprises an independent plate line, and in order to ensure the correctness of reading and writing, the invention also provides a plate line voltage generating circuit, so that the plate line voltage is at least 1 Vt less than the power supply voltage. When reading and writing operation is carried out, firstly, a storage control instruction is analyzed through a selection signal generation circuit, address information is obtained, then, according to the address information, a second selection circuit is controlled to select a corresponding sector (sector), then, a first selection circuit is controlled to select a corresponding byte storage unit, and the reading and writing operation is realized byte by byte. Compared with the existing ferroelectric memory, the ferroelectric memory provided by the invention not only reduces the complexity of the circuit, but also can save a large amount of wiring space, so that the size of the ferroelectric memory is optimized, and the storage with larger capacity can be realized on a smaller size.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various combinations, modifications, and changes can be made thereto without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims (10)
1. A ferroelectric memory, comprising:
the memory comprises a plurality of byte memory units, a plurality of bit lines and a plurality of plate lines, wherein each byte memory unit comprises a plurality of memory units, each memory unit comprises a bit line and a plate line, and the plate lines of the byte memory units are mutually independent; and
a first selection circuit including a plurality of first selection sub-circuit blocks, each of the first selection sub-circuit blocks having one end electrically connected to a bit line of a respective one of the memory cells of each of the byte memory cells and the other end connected to a plurality of corresponding sensing circuits, wherein:
the sensing circuit outputs sensing signals according to input signals of bit lines of the connected memory units, and when the first selection sub-circuit module corresponding to any byte memory unit is turned on, the first selection sub-circuit modules corresponding to the rest byte memory units are turned off, so that the bit line of only one byte memory unit is electrically connected to the sensing circuit each time.
2. The ferroelectric memory according to claim 1, wherein the sensing circuit comprises a plurality of sense amplifiers, and when a byte memory cell is selected, first input terminals of the sense amplifiers are sequentially electrically connected to bit lines of the respective memory cells of the byte memory cell through the first selection sub-circuit block, and second input terminals are electrically connected to corresponding reference lines of the bit lines through the first selection sub-circuit block or directly.
3. The ferroelectric memory of claim 1, wherein the first selection sub-circuit block includes a plurality of selection switches, each of which has one end connected to one of the bit lines and the other end connected to the sensing circuit.
4. A ferroelectric memory as in claim 3, wherein said selection switch comprises:
an inverter having an input coupled to the selection signal generation circuit;
a first switching transistor having a gate coupled to the selection signal generation circuit; and
a second switching transistor having a gate coupled to an output of the inverter.
5. The ferroelectric memory according to claim 4, wherein the signal generation circuit comprises:
a command decoder configured to encode according to a storage control instruction, forming a storage address; and
an address decoder communicably connected to the command decoder and configured to decode upon receiving the memory address, generating a selection signal.
6. The ferroelectric memory of claim 1, further comprising a plate line voltage generating circuit, the plate line voltage generating circuit comprising:
a first transistor having a first terminal connected to an input voltage and a gate coupled to the first terminal;
a linear voltage stabilizing module, an input end of which is connected to the second end of the first transistor; and
and the voltage division module is connected in series with the second end of the first transistor and is connected to the ground wire, wherein the first end of the first transistor refers to the source electrode or the drain electrode of the first transistor.
7. The ferroelectric memory of claim 6, wherein the linear regulator block comprises an operational amplifier having a positive input connected to the second terminal of the first transistor and a negative input connected to the output of the amplifier; and/or
The voltage division module comprises a second transistor or a resistor, wherein the first end of the second transistor or the resistor is connected to the second end of the first transistor, the second end of the second transistor or the resistor is grounded, and the grid electrode of the second transistor is coupled to the bias circuit, wherein the first end of the second transistor refers to the source electrode or the drain electrode of the first transistor.
8. The ferroelectric memory according to any one of claims 1 to 7, further comprising a plurality of sectors, wherein each of the sectors includes N-byte memory cells, all bit lines in each sector are connected to the plurality of bit line coupling lines in a one-to-one correspondence by one second selection sub-circuit block, and when the second selection sub-circuit block corresponding to any one sector is turned on, the second selection sub-circuit blocks corresponding to the remaining sectors are turned off, and the sensing circuit is connected to the bit line coupling line through the first selection sub-circuit block.
9. The ferroelectric memory according to claim 8, wherein the second selection sub-circuit block includes a plurality of the selection switches, the bit lines being connected to bit line coupling lines through the selection switches in one-to-one correspondence.
10. A method of operating a ferroelectric memory as in claim 8, comprising the steps of:
according to the selection signal, controlling the corresponding second selection sub-circuit module to be switched on, enabling the rest second selection sub-circuit modules to be switched off, and selecting a bit line of a storage unit of one sector to be connected to the bit line coupling line; and
and controlling the corresponding first selection sub-circuit module to be switched on according to the selection signal, switching off the other first selection sub-circuit modules, and selecting a bit line coupling line of one byte storage unit to be connected to the sensing circuit to read and write the byte at the designated position.
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