CN216849329U - Memory and electronic equipment - Google Patents

Abstract

The utility model discloses a memory and electronic equipment, wherein, this memory includes: the word line delay phase-locked loop circuit comprises a word line delay phase-locked loop, a first word line driver, a second word line driver, a reading circuit and a storage unit array; the word line delay phase-locked loop is respectively connected with the first word line driver and the second word line driver; the first word line driver is connected with the first end of the word line, and the second word line driver is connected with the second end of the word line; the memory cell array is connected with the read-out circuit through a bit line; the word line delay phase-locked loop simultaneously controls and sends a word line clock signal to the first word line driver and the second word line driver; the first word line driver and the second word line driver simultaneously supply a word line driving signal to the word lines, and the read circuit reads a signal through the bit lines. The utility model discloses can eliminate the drive signal of word line distal end and the drive signal's of word line near-end delay difference, improve the reading speed of memory.

Description

Memory and electronic equipment

Technical Field

The present disclosure relates to electronic circuits, and particularly to a memory and an electronic device.

Background

Memories are widely used in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Memory cells of a memory are programmed to various states to store information. For example, a binary memory cell can be programmed to one of two states corresponding to a logic 1 or a logic 0. To access information stored by the memory, the component may read or sense the state of one or more memory cells within the memory.

At present, the memory cell array of various memories is very large, the position of the memory cell influences the speed of reading the value, the word line WL of the memory cell close to the word line driver is opened earlier, and the word line WL of the memory cell far away from the word line driver is opened later. In addition, the sense amplifiers SA are arranged along a whole edge of the memory cell array, and SA close to the control signal driver is turned on earlier, SA far from the control signal driver is turned on later, and the control signal is delayed from left to right, so that the read speed of the memory cell array is slow.

It is noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure and therefore may include information that does not constitute prior art that is already known to a person of ordinary skill in the art.

SUMMERY OF THE UTILITY MODEL

The present disclosure provides a memory and an electronic device, which overcome, at least to some extent, the problem of delay difference between both ends of a word line WL in the related art.

Additional features and advantages of the disclosure will be set forth in the detailed description which follows, or in part will be obvious from the description, or may be learned by practice of the disclosure.

The embodiment of the utility model provides a memory, include: the memory comprises a memory cell array, a word line, a first word line driver, a second word line driver, a word line delay phase-locked loop and a reading circuit; a first word line driver connected to a first end of the word line; a second word line driver connected to a second end of the word line; the first word line driver responds to a first clock signal to generate a first word line driving signal, the word line delay phase-locked loop receives the first clock signal to generate a second clock signal which is consistent with the phase of the first clock signal, and the second word line driver responds to the second clock signal to generate a second word line driving signal.

Preferably, the first word line driver is located at a first side of the memory cell array, and the second word line driver is located at a second side of the memory cell array.

Preferably, the word line delay locked loop is located at a second side of the memory cell array.

Preferably, the word line driver further comprises a clock generation circuit, the clock generation circuit generates the first clock signal, and a distance between the clock generation circuit and the first word line driver is smaller than a distance between the clock generation circuit and the second word line driver.

Preferably, the first clock signal and the second clock signal are aligned clock signals.

Preferably, the method further comprises the following steps: the readout circuit comprises a delay phase-locked loop of a readout circuit, a first readout circuit driver and a second readout circuit driver; the readout circuit comprises a plurality of sense amplifiers, the sense amplifiers are connected with a control signal line, a first readout circuit driver is connected with a first end of the control signal line, a second readout circuit driver is connected with a second end of the control signal line, the first readout circuit driver generates a first control signal in response to a third clock signal, a readout circuit delay phase-locked loop receives the third clock signal and generates a fourth clock signal, and the second readout circuit driver generates a second control signal in response to the fourth clock signal.

Preferably, the third clock signal and the fourth clock signal are aligned clock signals.

Preferably, the memory is a dynamic random access memory, a static random access memory, a magnetic random access memory or a resistive random access memory.

Preferably, the plurality of sense amplifiers are arranged in a row arrangement.

An electronic device comprises the memory.

The utility model discloses a memory and electronic equipment, wherein, this memory includes: the word line delay phase-locked loop comprises a word line delay phase-locked loop, a first word line driver, a second word line driver, a reading circuit and a storage unit array; the word line delay phase-locked loop is respectively connected with the first word line driver and the second word line driver; the first word line driver is connected with the first end of the word line, and the second word line driver is connected with the second end of the word line; the memory cell array is connected with the read-out circuit through a bit line; the word line delay phase-locked loop simultaneously controls and sends a word line clock signal to the first word line driver and the second word line driver; the first word line driver and the second word line driver simultaneously supply a word line driving signal to the word lines, and the read circuit reads a signal through the bit lines. The utility model discloses can eliminate the drive signal of word line distal end and the drive signal's of word line near-end delay difference, improve the reading speed of memory.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

FIG. 1 is a schematic diagram of a memory according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a first word line driving signal Drive1 and a second word line driving signal Drive2 according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a memory according to another embodiment of the present invention;

fig. 4 is a schematic diagram of a sense amplifier SA according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a DRAM memory cell;

FIG. 6 is a schematic diagram of an RRAM memory cell.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities.

The embodiment of the present invention provides a memory, fig. 1 is the embodiment of the present invention provides a schematic diagram of a memory, as shown in fig. 1, this memory 10 includes: a memory cell array 105, a word line WL, a first word line driver 102, a second word line driver 103, a word line delay locked loop 101, and a readout circuit 104; the first word line driver 102 is connected to a first end of the word line WL; the second word line driver 103 is connected to a second end of the word line WL; the first word line driver 102 generates a first word line driving signal in response to a first clock signal, the word line delay locked loop 101 receives the first clock signal to generate a second clock signal having a phase identical to that of the first clock signal, and the second word line driver 103 generates a second word line driving signal in response to the second clock signal.

In one embodiment, memory 10 also includes clock generation circuitry and word line decoders. The clock generation circuit provides a first clock signal CLK 1. The first wordline driver 102 generates a first wordline Drive signal Drive1 in response to a first clock signal CLK 1. The wordline dll 101 receives the first clock signal CLK1 to generate a second clock signal CLK2 that is in phase with the first clock signal CLK1, and the second wordline driver 103 generates a second wordline Drive signal Drive2 in response to the second clock signal CLK 2. The word line decoder is used for selecting a target bit line according to an address signal, thereby transmitting a word line driving signal to the target bit line.

In one embodiment, the first wordline driver 102 is located on a first side of the memory cell array 105 and the second wordline driver 103 is located on a second side of the memory cell array 105. The first word line driver 102 is connected to a first end of the word line WL, and the second word line driver 103 is connected to a second end of the word line WL. The word line delay locked loop 101 is also located on a second side of the memory cell array 105. The clock generation circuit is located on a first side of the memory cell array 105. The distance from the clock generation circuit to the first word line driver 102 is smaller than the distance from the clock generation circuit to the second word line driver 103. The first clock signal CLK1 generated by the clock generation circuit is sent to the first wordline driver 102 through a first signal line and to the wordline delay locked loop 101 through a second signal line. The second clock signal CLK2 generated by the wordline delay locked loop 101 is sent to the second wordline driver 103 through a third signal line.

It should be noted that, a Delay-Locked Loop (DLL) is used to automatically adjust the Delay of one signal, so that the phases of two signals are consistent (edges are aligned). The delay locked loop can align the edges of two clocks, and the regulated clock is used as a control signal to generate a signal strictly synchronous with the system clock, and the synchronization does not change along with the change of external conditions such as temperature and voltage, so the delay locked loop can be widely used. The output clock is matched to the phase of the input clock by a feedback loop. In the feedback loop, the phase difference between the input clock and the output clock is determined by a phase detector.

The clock generation circuit is disposed near the first word line driver 102, and the word line delay locked loop 101 is disposed near the second word line driver 103. In the case where the memory cell array is large, the second signal line is long, and the transfer of the first clock signal CLK1 to the second side of the memory cell array causes a delay. If the second wordline driver 103 is directly triggered by the first clock signal CLK1, the first wordline driver 102 and the second wordline driver 103 cannot generate wordline drive signals simultaneously.

In the above embodiment, by providing the word line delay locked loop 101, the second clock signal CLK2 is aligned with the first clock signal CLK1, and the first word line driver 102 and the second word line driver 103 generate the word line driving signals simultaneously, that is, the first end and the second end of the target word line WL receive the word line driving signals simultaneously, the problem of excessive time difference of the opening of the memory cells in the same row caused by applying the word line driving signals from only one end of the word line WL is solved.

FIG. 2 shows a first word line driving signal Drive1 and a second word line driving signal Drive 2. As shown in fig. 2, the first word line driving signal Drive1 generated by the first word line driver 102 and the second word line driving signal Drive2 generated by the second word line driver 103 are aligned, and the frequencies, start times, and the like of the two signals are kept consistent. The first word line driver 102 transmits the generated first word line driving signal Drive1 to the memory cell array 105 through the word line WL; the second word line driver 103 transmits a second word line driving signal Drive2 to the memory cell array 105 through the word line WL, so that the transistor T1 or the transistor T3 in a row of memory cells corresponding to the word line WL can be turned on. The sense circuit 104 includes a plurality of Sense Amplifiers (SA) 1041, the plurality of sense amplifiers 1041 are connected to the memory cell array 105 through bit lines BL, and the sense amplifiers 1041 sense information stored in the memory cells.

It should be noted that WL can be any WLi from WL0 to WLN 1, where i is any value from 0 to N1.

In the above embodiment, the word line delay locked loop 101, the first word line driver 102 and the second word line driver 103 simultaneously apply the generated word line driving signals to the word lines WL, so as to eliminate the delay difference between the far ends of the word lines WL and the near ends of the word lines WL, thereby improving the reading speed of the memory 10; and the area overhead of the word line delay locked loop 101 is about 0.1%, so that the cost is saved.

Fig. 3 is a schematic diagram of another memory according to an embodiment of the present invention, and as shown in fig. 3, the memory 10 further includes: a readout circuit delay locked loop 108, a first readout circuit driver 106, and a second readout circuit driver 107.

The sense circuit 104 is connected to one end of the bit line BL; the readout circuit 104 includes a plurality of sense amplifiers 1041, the plurality of sense amplifiers 1041 are connected to the control signal line, the first readout circuit driver 106 is connected to a first end of the control signal line, the second readout circuit driver 107 is connected to a second end of the control signal line, the first readout circuit driver 106 generates the first control signal in response to the third clock signal, the readout circuit delay locked loop 108 receives the third clock signal to generate the fourth clock signal, and the second readout circuit driver 107 generates the second control signal in response to the fourth clock signal.

In one embodiment, the plurality of sense amplifiers 1041 of the sensing circuit 104 are disposed generally on one side of the memory cell array 105, such as a third side of the memory cell array 105. The plurality of sense amplifiers 1041 of the sensing circuit 104 are generally arranged in a row, and each sense amplifier 1041 is connected to a corresponding bit line BL. For RRAM or MRAM, each sense amplifier 1041 is connected to a corresponding one of the bit lines BL. For a DRAM, each sense amplifier 1041 connects a corresponding two bit lines BL. The read operation and the program operation (write operation) of the memory 10 are generally performed in units of one row of memory cells, and the plurality of sense amplifiers 1041 of the sense circuit 104 operate simultaneously. The plurality of sense amplifiers 1041 are connected to the same control signal line, the first readout circuit driver 106 is connected to a first end of the control signal line, the second readout circuit driver 107 is connected to a second end of the control signal line, the first readout circuit driver 106 generates the first control signal in response to the third clock signal CLK3, the readout circuit delay locked loop 108 receives the third clock signal CLK3 to generate the fourth clock signal CLK4, and the second readout circuit driver 107 generates the second control signal in response to the fourth clock signal CLK 4. The control signal is, for example, an enable signal or a start signal of the sense amplifier 1041. The fourth clock signal CLK4 is a clock signal that is aligned with the third clock signal CLK 3. The third clock signal CLK3 is also generated by a clock generation circuit, for example, the first readout circuit driver 106 is closer to the clock generation circuit, and the second readout circuit driver 107 is farther from the clock generation circuit. The first readout circuit driver 106 and the second readout circuit driver 107 can simultaneously generate and supply control signals to the control signal lines of the plurality of sense amplifiers 1041 by the readout circuit delay locked loop 108.

Note that the frequencies, start times, and the like of the first control signal and the second control signal coincide with each other.

In the above embodiment, the memory provided in the embodiment of the present invention respectively sets the first word line driver 102 and the second word line driver 103 at two ends of the word line WL, and the word line delay phase-locked loop 101 enables the first word line driver 102 and the second word line driver 103 to simultaneously transmit the word line driving signal to the word line WL, so that the delay difference of the driving signals at the near end and the far end of the word line WL is eliminated, and the reading speed of the memory is improved. Furthermore, a first readout circuit driver 106 and a second readout circuit driver 107 are respectively arranged at two ends of a control signal line of the readout circuit 104, and the first readout circuit driver 106 and the second readout circuit driver 107 are enabled to simultaneously send readout circuit driving signals to the control signal line through a readout circuit delay locked loop 108, so that the delay difference of the driving signals at the near end and the far end of the control signal line is eliminated, and the readout speed of the memory is improved.

Fig. 4 is a schematic diagram of a sense amplifier according to an embodiment of the present invention, which is suitable for an RRAM memory and an MRAM memory. As shown in fig. 4, the sense amplifier 1041 compares the magnitude of the current Icell of the sensed memory cell with the magnitude of the reference current IREF of the reference cell; the sense amplifier 1041 is connected to a sensed memory cell through a bit line BL.

It should be noted that BL can be any BLi from BL0 to BLN-1, and sense amplifier 1041 can be a corresponding sense amplifier SAi, where i is any value from 0 to N-1. It should be noted that the operation includes, but is not limited to, a read operation, an erase verify operation or a program verify operation; the reference current IREF generated by the reference cell is supplied to the sense amplifier 1041 through the current mirror circuit.

The memory 10 is one of a dynamic random access memory, a static random access memory, a magnetic random access memory, and a resistive random access memory.

In one embodiment, memory 10 is, for example, a DRAM. FIG. 5 is a schematic diagram of a DRAM memory cell. Each DRAM memory cell 1051 includes a transistor T1 and a capacitor C. The first terminal of the capacitor C is set to a common level, e.g. low or half the supply voltage. The second terminal of the capacitor C is connected to the corresponding bit line BL through the transistor T1. The gate of the transistor T1 is connected to the word line WL. When the second end of the capacitor C is the power supply voltage, the storage unit stores logic 1; when the second terminal of the capacitor C is at a low level, the memory cell stores a logic 0.

In one embodiment, for a DRAM memory, the sense amplifiers 1041 include, but are not limited to, differential amplifiers or latch-type amplifiers.

In one embodiment, memory 10 is, for example, a RRAM or a MARM. RRAM and MARM are semiconductor memories that have emerged in recent years. Because it has the advantages of high integration level, high read-write speed, low power consumption, compatibility with a Complementary Metal-Oxide-Semiconductor (CMOS) process, etc., it is considered by more and more people as the best choice for the next generation of mainstream nonvolatile memories. The RRAM has the working principle that voltages with different polarities or different magnitudes are applied to two ends of the resistance change material to control the resistance value of the resistance change material to be switched between a High Resistance State (HRS) and a Low Resistance State (LRS). Different states can be distinguished according to different resistance values, so that logic 0 and logic 1 are realized. In general, the transition from the high resistance state to the low resistance state is referred to as SET (i.e., SET), and the transition from the low resistance state to the high resistance state is referred to as RESET (i.e., RESET). FIG. 6 is a schematic diagram of an RRAM memory cell. Each RRAM memory cell 1052 includes a transistor T3 and a resistive switching element R. The resistive switching element R includes a top electrode, a bottom electrode, and a data storage structure (e.g., one or more oxide layers) disposed between the top electrode and the bottom electrode. The source of the transistor T3 is connected to the source line SL, the gate of the transistor T3 is connected to the word line WL, the drain of the transistor T3 is connected to the bottom electrode of the resistive element R, and the top electrode of the resistive element R is connected to the bit line BL. The grid electrode of the transistor of each row of resistive random access units is connected to the same word line WL. The source electrode of the transistor of each row of resistive random access units is connected to the same source line SL, and the top electrode of the transistor is connected with the same bit line BL.

Operations of the memory 10, such as a read operation and a program operation (also referred to as a write operation), are generally performed in units of rows. For example, when a word line drive signal is applied to a certain word line WL, data is written into a row of memory cells corresponding to the word line WL through the bit line BL, or data in the row of memory cells corresponding to the word line WL is read through the bit line BL.

The memory 10 further comprises: the controller 111 is connected to the row decoder and the column decoder 110, the controller 111 sends control signals to the row decoder and the column decoder 110, and the controller 111 addresses selection signals through the row decoder and the column decoder 110.

The memory 10 further comprises: an interface circuit 109; the memory 10 is electrically connected to the host 20 through the interface circuit 109. The memory 10 may be a built-in or external storage device of the host 20. It should be noted that the host 20 is a device of a user, and the host 20 includes, but is not limited to, a mobile phone, a tablet, a notebook, a camera, and the like.

It should be noted that the memory 10 performs bidirectional data communication with the host 20, and the communication standards of the memory 10 and the host 20 are, for example, Serial Advanced Technology Attachment (SATA) standard, Parallel Advanced Technology Attachment (PATA) standard, Universal Serial Bus (USB) standard, Secure Digital (SD) interface standard, Multimedia Memory Card (MMC) interface standard, serial peripheral interface (DDR) standard, double data rate standard (DDR) and the like.

The memory 10 may respond to a requested operation from the host 20. For example, the memory 10 may store data provided by the host 20 and may also provide the stored data to the host 20. The data stored in the memory 10 is accessible to the host 20. The memory 10 may be used as the primary memory 10 or the secondary memory 10 of the host 20. Here, the data stored in the memory 10 may include not only a narrow data file (e.g., a photograph taken, a Word document written, etc.) but also other data in a broad sense, such as command data and address data, etc. Memory cell array 105 includes memory cells arranged in a plurality of rows and columns. The Memory 10 may be a non-volatile Memory such as a Flash Memory (Flash), a Magnetic Random Access Memory (MRAM), a Resistive Random Access Memory (RAM), and the like. The Memory 10 may also be a volatile Memory, such as a Dynamic Random Access Memory (DRAM), a Static Random-Access Memory (SRAM), and the like. The memory cells are addressed by word lines WL and bit lines BL. The memory cells in the same row are connected to the same word line, and the memory cells in the same column are connected to the same bit line.

The utility model also provides an electronic equipment, including as above memory 10.

The above embodiments, further detailed description of the objects, technical solutions and advantages of the present invention, it should be understood that the above embodiments are only specific embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (10)

1. A memory, comprising:

a memory cell array (105);

a word line;

a first word line driver (102) connected to a first end of the word line;

a second word line driver (103) connected to a second end of the word line;

a word line delay locked loop (101);

a readout circuit (104);

wherein the first word line driver (102) generates a first word line driving signal in response to a first clock signal, the word line delay locked loop (101) receives the first clock signal to generate a second clock signal in phase with the first clock signal, and the second word line driver (103) generates a second word line driving signal in response to the second clock signal.

2. The memory of claim 1, wherein the first wordline driver (102) is located on a first side of the memory cell array (105) and the second wordline driver (103) is located on a second side of the memory cell array (105).

3. The memory of claim 2, wherein the word line delay locked loop (101) is located on a second side of the memory cell array (105).

4. The memory of claim 1, further comprising a clock generation circuit that generates the first clock signal, the clock generation circuit being located a distance from the first word line driver (102) that is less than a distance from the clock generation circuit to the second word line driver (103).

5. The memory of claim 1, wherein the first clock signal and the second clock signal are aligned clock signals.

6. The memory of claim 1, further comprising: a readout circuit delay locked loop (108), a first readout circuit driver (106), and a second readout circuit driver (107); the readout circuit (104) comprises a plurality of sense amplifiers (1041), the plurality of sense amplifiers (1041) are connected with a control signal line, a first readout circuit driver (106) is connected with a first end of the control signal line, a second readout circuit driver (107) is connected with a second end of the control signal line, the first readout circuit driver (106) generates a first control signal in response to a third clock signal, a readout circuit delay-locked loop (108) receives the third clock signal to generate a fourth clock signal, and the second readout circuit driver (107) generates a second control signal in response to the fourth clock signal.

7. The memory of claim 6, wherein the third clock signal and the fourth clock signal are aligned clock signals.

8. The memory of claim 1, wherein the memory is a dynamic random access memory, a static random access memory, a magnetic random access memory, or a resistive random access memory.

9. The memory of claim 6, wherein the plurality of sense amplifiers (1041) are arranged in a row arrangement.

10. An electronic device comprising the memory of any one of claims 1-9.

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