KR910001779A - RAM test method and circuit of memory device - Google Patents

RAM test method and circuit of memory device Download PDF

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Publication number
KR910001779A
KR910001779A KR1019890008002A KR890008002A KR910001779A KR 910001779 A KR910001779 A KR 910001779A KR 1019890008002 A KR1019890008002 A KR 1019890008002A KR 890008002 A KR890008002 A KR 890008002A KR 910001779 A KR910001779 A KR 910001779A
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KR
South Korea
Prior art keywords
bit line
control circuit
data
output
checking
Prior art date
Application number
KR1019890008002A
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Korean (ko)
Other versions
KR920001080B1 (en
Inventor
최훈
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019890008002A priority Critical patent/KR920001080B1/en
Priority to FR9001203A priority patent/FR2648266B1/en
Priority to DE4003132A priority patent/DE4003132A1/en
Priority to GB9002396A priority patent/GB2232496B/en
Priority to JP02022322A priority patent/JP3101953B2/en
Priority to NL9000261A priority patent/NL194812C/en
Priority to SE9002030A priority patent/SE512452C2/en
Priority to IT02056690A priority patent/IT1248750B/en
Priority to SU904830256A priority patent/RU2084972C1/en
Priority to CN90104915A priority patent/CN1019243B/en
Publication of KR910001779A publication Critical patent/KR910001779A/en
Priority to US07/827,578 priority patent/US5197031A/en
Application granted granted Critical
Publication of KR920001080B1 publication Critical patent/KR920001080B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/34—Accessing multiple bits simultaneously
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/36—Data generation devices, e.g. data inverters

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

내용 없음No content

Description

메모리소자의 램 테스트 방법 및 회로RAM test method and circuit of memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 실시회로도이다.1 is an exemplary circuit diagram of the present invention.

Claims (5)

비트라인(B/L),()에 공급되는 전원(VCC)을 콘트롤 회로(1)에서 제어하여 메모리용 캐패시터(C1)에 데이타를 기록하는 방법; 메모리용 캐패시터(C1)에서 데이타의 인출시 센서앰프(2)를 통하여 비트라인(B/L), ()의 출력이 증폭되게 한 리드(READ)방법; 상기 리드방법에 의한 비트라인(B/L), ()의 출력과, 콘트롤회로(1)의 래치된 출력에 의하여 체크회로(3)에서 에러상태가 검사되도록 한 체크방법;를 포함하는 메모리소자의 램 테스트 방법.Bit line (B / L), ( Controlling the power supply VCC supplied to the control circuit 1 in the control circuit 1 to write data into the memory capacitor C1; The bit line (B / L), through the sensor amplifier (2) at the time of withdrawing data from the memory capacitor (C1) ( READ method for amplifying the output of the; Bit line (B / L) by the read method, ( And a check method for checking an error state in the check circuit (3) by the output of the control circuit and the latched output of the control circuit (1). 제1항에 있어서, 메모리용 캐패시터(C1)에 데이타를 기록하는 방법은, 워드라인(W/L)을 선택한 후 콘트롤 회로(1)의 노우드의 출력을 제어하여 직접 메모리용 캐패시터(C1)에 저장하는 방법과, 비트라인(B/L),()에 직접 기록하기 비트라인(B/L), ()에 직접 기록하기 위한 MOS트랜지스터(M2), (M4)를 선택하여 비트라인 (B/L), ()사이에서 발생되는 전압차를 센스앰프(2)에서 증폭시켜 비트라인이 전원(VCC) 레벨로 되게 하여 워드라인 선택후 메모리용 캐패시터(C1)에 저장하는 방법과, 를 포함하는 메모리소자의 램 테스트 방법.The method of claim 1, wherein the method of writing data to the memory capacitor C1 includes selecting the word line W / L and controlling the output of the nord of the control circuit 1 to directly control the capacitor C1. To a bit line (B / L), ( Write directly to) Bitline (B / L), ( Select the MOS transistors (M2) and (M4) for direct writing to the bit lines (B / L), ( And amplifying the voltage difference generated by the sense amplifier 2 to bring the bit line to the power supply (VCC) level, selecting the word line, and storing the difference in the memory capacitor C1. Testing method. 비트라인(B/L), ()에 연결되어 감지된 상태신호를 출력시키는 센스앰프(2)와, 워드라인(W/L) 및 비트라인(B/L)에 연결된 메모리 셀(5)과, 컬럼선택신호(COL)에 의하여 턴온되어 입출력라인(I/O)이 비트라인(B/L), ()과 연결되게 한 MOS 트랜지스터(M9), (M10)와, 구성된 DRAM 회로에 있어서, 상기 비트라인(B/L), ()에 연결되어 비트라인을 전원(VCC) 레벨 및 접지레벨로 유지시키어 데이타를 기록하는 수단과, 센스앰프(2) 후단에 연결되어 리드(READ)된 데이타를 체크하는 수단과, 상기 데이타를 기록하는 수단 및 체크하는 수단을 제어하는 콘트롤회로(1)와, 로 구성된 메모리소자의 램 데스트 회로.Bit line (B / L), ( Is connected to the sense amplifier 2 to output the sensed state signal, the memory cell 5 connected to the word line W / L and the bit line B / L, and the column select signal COL. Turned on and the input / output line (I / O) becomes bit line (B / L), ( MOS transistors (M9) and (M10) connected to each other, and a DRAM circuit comprising: the bit lines (B / L), ( Means for recording the data by maintaining the bit line at the power supply (VCC) level and the ground level; and means for checking the read data connected to the rear end of the sense amplifier (2), and recording the data. And a control circuit (1) for controlling means for checking and means for checking. 제3항에 있어서, 데이타를 기록하는 수단은 상기 비트라인(B/L), ()에 연결되어 전원(VCC)레벨이 유지되도록 전원을 공급하는 PMOS 트랜지스터(M1), (M3)와, 상기 비트라인(B/L),()에 연결되어 접지레벨을 유지시키는 NMOS 트랜지스터(M2), (M4)와, 상기 MOS 트랜지스터(M1-M4)의 구동을 제어하는 콘트롤회로(1)와로 구성된 메모리소자의 램 테스트 회로.4. The apparatus according to claim 3, wherein the means for recording data comprises the bit line (B / L), ( PMOS transistors M1 and M3 connected to the PMOS transistors M1 and M3 to supply power to maintain the power supply VCC level. And a control circuit (1) for controlling the driving of the MOS transistors (M1) and (M4) for maintaining a ground level. 제3항에 있어서, 데이타를 체크하는 수단은 비트라인(B/L), ()에 게이트축이 연결된 PMOS 트랜지스터(M5), (M6)와, 상기 NMOS 트랜지스터(M5), (M6)에 래치된 출력을 공급하는 콘트롤회로(1)와, NMOS 트랜지스터(M5),(M6)사이에 연결되어 데이타 체크 에러상태에 따라 구동되는 NMOS 트랜지스터(M8)와, 로 구성된 메모리소자의 램 테스트 회로.4. The apparatus of claim 3, wherein the means for checking data comprises: bit line (B / L), ( PMOS transistors M5 and M6 connected to gate axes, a control circuit 1 for supplying the latched outputs to the NMOS transistors M5 and M6, and NMOS transistors M5 and M6. A RAM test circuit of a memory device comprising an NMOS transistor (M8) connected between and driven according to a data check error state. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890008002A 1989-06-10 1989-06-10 Method writing data and test circuit in memory material KR920001080B1 (en)

Priority Applications (11)

Application Number Priority Date Filing Date Title
KR1019890008002A KR920001080B1 (en) 1989-06-10 1989-06-10 Method writing data and test circuit in memory material
FR9001203A FR2648266B1 (en) 1989-06-10 1990-02-01 METHOD FOR WRITING DATA WHEN TESTING A MEMORY DEVICE, AND MEMORY DEVICE TESTING CIRCUIT
GB9002396A GB2232496B (en) 1989-06-10 1990-02-02 A test circuit for testing a memory device and methods for performing writing and testing in such devices
JP02022322A JP3101953B2 (en) 1989-06-10 1990-02-02 Memory circuit having test function of recording element
DE4003132A DE4003132A1 (en) 1989-06-10 1990-02-02 METHOD FOR WRITING DATA INTO A TEST STORAGE DEVICE AND CIRCUIT FOR TESTING A STORAGE DEVICE
NL9000261A NL194812C (en) 1989-06-10 1990-02-02 Circuit for testing a memory device.
SE9002030A SE512452C2 (en) 1989-06-10 1990-06-06 Method for writing data when testing memory device and circuit for testing memory device
IT02056690A IT1248750B (en) 1989-06-10 1990-06-07 METHOD FOR STORING DATA IN A TEST OF A MEMORY DEVICE AND CIRCUIT FOR TESTING A MEMORY DEVICE
SU904830256A RU2084972C1 (en) 1989-06-10 1990-06-08 Method for writing data when memory unit is being tested and memory-testing device
CN90104915A CN1019243B (en) 1989-06-10 1990-06-09 Method for writing data in testing memory device and circuit for testing memory device
US07/827,578 US5197031A (en) 1989-06-10 1992-01-29 Method for writing data in testing memory device and circuit for testing memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890008002A KR920001080B1 (en) 1989-06-10 1989-06-10 Method writing data and test circuit in memory material

Publications (2)

Publication Number Publication Date
KR910001779A true KR910001779A (en) 1991-01-31
KR920001080B1 KR920001080B1 (en) 1992-02-01

Family

ID=19286971

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890008002A KR920001080B1 (en) 1989-06-10 1989-06-10 Method writing data and test circuit in memory material

Country Status (10)

Country Link
JP (1) JP3101953B2 (en)
KR (1) KR920001080B1 (en)
CN (1) CN1019243B (en)
DE (1) DE4003132A1 (en)
FR (1) FR2648266B1 (en)
GB (1) GB2232496B (en)
IT (1) IT1248750B (en)
NL (1) NL194812C (en)
RU (1) RU2084972C1 (en)
SE (1) SE512452C2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05128899A (en) * 1991-10-29 1993-05-25 Mitsubishi Electric Corp Semiconductor memory
US6950356B2 (en) * 2002-02-26 2005-09-27 Koninklijke Philips Electronics N.V. Non-volatile memory test structure and method
RU2681344C1 (en) * 2015-03-09 2019-03-06 Тосиба Мемори Корпорейшн Semiconductor storage device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59185097A (en) * 1983-04-04 1984-10-20 Oki Electric Ind Co Ltd Memory device with self-diagnostic function
JPS62229599A (en) * 1986-03-31 1987-10-08 Toshiba Corp Nonvolatile semiconductor memory device
EP0253161B1 (en) * 1986-06-25 1991-10-16 Nec Corporation Testing circuit for random access memory device
KR910001534B1 (en) * 1986-09-08 1991-03-15 가부시키가이샤 도시바 Semiconductor memory device
JPS6446300A (en) * 1987-08-17 1989-02-20 Nippon Telegraph & Telephone Semiconductor memory
JPH01113999A (en) * 1987-10-28 1989-05-02 Toshiba Corp Stress test circuit for non-volatile memory

Also Published As

Publication number Publication date
SE9002030L (en) 1990-12-11
NL9000261A (en) 1991-01-02
FR2648266B1 (en) 1993-12-24
JP3101953B2 (en) 2000-10-23
GB2232496B (en) 1993-06-02
NL194812C (en) 2003-03-04
GB2232496A (en) 1990-12-12
IT9020566A0 (en) 1990-06-07
NL194812B (en) 2002-11-01
GB9002396D0 (en) 1990-04-04
CN1048463A (en) 1991-01-09
IT9020566A1 (en) 1991-12-07
IT1248750B (en) 1995-01-27
FR2648266A1 (en) 1990-12-14
DE4003132C2 (en) 1992-06-04
SE512452C2 (en) 2000-03-20
KR920001080B1 (en) 1992-02-01
JPH0312100A (en) 1991-01-21
DE4003132A1 (en) 1990-12-20
CN1019243B (en) 1992-11-25
RU2084972C1 (en) 1997-07-20
SE9002030D0 (en) 1990-06-06

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