JP2831683B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] With respect to a semiconductor memory device, an object of the present invention is to provide a semiconductor memory device capable of performing a function test in a short time at a low cost with a simple configuration. Detecting means for detecting a bit line defect based on an output of the potential detecting means, the potential detecting means including a detecting node and a first transistor; Is connected to a first power supply via a second transistor, the drain of the first transistor is connected to a second power supply, the source of the first transistor is connected to the detection node, The gate of the first transistor is connected to the bit line, and when the bit line is defective, the first transistor is turned on to change the potential of the detection node to the second voltage. The potential of the bit line is raised to the potential of the power supply, and the failure determination means determines the failure of the bit line.

[Industrial applications]

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device for shortening a test time of a large-capacity memory.

In testing a memory LSI, a test technique having various features is used. That is, a memory LSI has a memory cell and its peripheral circuits mounted on the same chip,
In the test of I, a functional test for testing the operation of these circuits occupies the most important position, and various test patterns are used. One of the electrical test methods of the memory LSI is a function test. In the RAM functional test, a test pattern composed of an input pattern such as an address, write data, a write / read signal and an output expected value pattern is generated and executed by a pattern generator dedicated to the RAM. In such a functional test, a short test time is desired.

[Conventional technology]

In the function test (function test) of conventional semiconductor memory (especially RAM), an expensive LSI memory tester is used, and it takes a long test time to perform a wafer probe test (test by directly applying a probe to the LSI pad). The test is performed before the product is shipped as a product, and the acceptance test is performed when the user accepts the product.

In particular, when a bit line or the like in the memory is short-circuited due to high resistance, a test having a long cycle time or a test using a special test pattern is required. In this case, the memory itself does not have a circuit to assist the test.

[Problems to be solved by the invention]

However, such a conventional semiconductor memory device does not have a special circuit for testing inside, for example, when a certain bit line has a high impedance and is short-circuited to another node. In addition, there is a problem in that the test time is long to detect this, and this is particularly remarkable in a large-capacity memory.

That is, in the above case, the bit line does not go to the normal level during the data write operation, so that the memory cell is stored at the intermediate level. On the other hand, in this case, the amount of information appearing on the bit line at the time of reading data is small, and is determined to be defective by a so-called disturb test or the like, or is determined to be defective by a long clock test.

FIG. 4 shows an example of the long clock test.
First, the signal {circle around (4)} falls, the memory access starts and the row address is fetched, then the signal {circle around (4)} falls to fetch the column address, and the address A is selected (ADD = A). Further, the signal ▲ is lowered to select data writing, and “1” is written to the address A as data (DATA). In order to reject a defect stored in a memory cell as an intermediate level as described above, the active time T _RAS for selecting an address A and writing data is long to facilitate detection of a bit line defect. It is set and several hundred μs is required. When the data writing to the address A is completed in this way, the address is advanced by [1] and the data of "0" is written (as A + 1). In this manner, data is sequentially written, and at the stage of a read test, data "1" is read from address A and checked, and then data "0" is read from address A + 1 and checked. At this time, if intermediate-level data is stored in the memory cell due to a defective bit line, “1” or “0”
It is not clear, this is determined by the test.

By the way, regardless of such a long clock test or a disturb test, especially when a large-capacity memory is used, the active time T _RAS becomes long as a whole, and eventually the test time becomes extremely long. Also, LSI memory testers are expensive.

Therefore, an object of the present invention is to provide a semiconductor memory device that can perform a functional test in a short time at a low cost with a simple configuration.

[Means for solving the problem]

The semiconductor memory device according to the present invention achieves the above object,
Potential detection means for detecting the potential of the bit line; and failure determination means for determining failure of the bit line based on the output of the potential detection means, wherein the potential detection means comprises a detection node and a first transistor. The detection node is connected to a first power supply via a second transistor, the drain of the first transistor is connected to a second power supply, and the source of the first transistor is connected to the detection power supply. And the gate of the first transistor is connected to the bit line, and when the bit line is defective, the first transistor is turned on to raise the potential of the detection node to the The potential of the bit line is raised to the potential of the second power supply, and the failure determination means determines the failure of the bit line.

[Action]

According to the present invention, the detection node of the potential detecting means is maintained in the initial state in advance, and when the potential from the memory cell shifts to the selected bit line at the time of data reading, the bit line is short-circuited to, for example, the ground potential. If there is such a defect, the first transistor is turned on and the potential of the detection node is raised to the potential of the second power supply. Then, the defect of the bit line is determined by the defect determining means based on the potential of the detection node.

Therefore, even if the potential at the time of selection is an intermediate level due to a bit line defect, the defect can be easily determined by the defect determination means, and a functional test can be performed in a short time with a simple test pattern.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

1 to 3 are views showing one embodiment of a semiconductor memory device according to the present invention. FIG. 1 shows a configuration diagram of a main part of a DRAM, in which WL ₁ , WL ₂ ... Are word lines, BL ₀ , ▲
▼, BL ₁ , ▲ ▼ ... are bit lines, 1a, 1b ... are sense amplifiers activated by latch enable (LE) signals,
.. And 3a, 3b... Are memory cells. As an example, the memory cell 2a is constituted by a transfer gate MOS transistor 4a and a capacitor cell 4b, and the same applies to other memory cells.

Reference numeral 5 denotes potential detecting means for detecting a potential corresponding to the defective state for each bit line. The potential detecting means 5 has a gate connected to the bit lines BL ₀ , BL ₁ , BL ₂ and a drain connected to the second. a high potential is connected to the power supply Vcc, further its source commonly connected to the detection node (hereinafter, simply node named) first P-channel included in the transistor MOS transistors 6a connected to NP ₁ constituting the power ~ 6c ……
And the gates are bit lines ▲ ▼, ▲ ▼, ▲
▼, its drain is connected to the high potential power supply Vcc, and its source is connected in common to the node NP
Configuration and MOS transistor 7a~7c ...... P-channel constituting the first transistor connected to _2, the second transistor closed by inserted the end portion of the nodes NP _1, NP ₂ reset (RST) signal N-channel MOS transistor Q
P _1, QP ₂ and the constructed. When a reset signal is applied to the gates of the MOS transistors QP ₁ and QP ₂ in advance before detecting a defect, the source and drain are closed and the nodes NP ₁ and NP ₂ are each in the initial state of the potential 0 V ( = Vss).

The nodes NP ₁ and NP ₂ are connected to discriminating circuits 8 and 9, respectively. The discriminating circuit 8 has an inverter 10, a NOR gate 11, and an external pin (corresponding to a pad) 12, and the discriminating circuit 9 includes an inverter 13 and a NOR gate 14. And external pins 15. Discriminating circuit 8 inverts the potential of the node NP ₁ by an inverter 10, which a strobe signal for comparison (hereinafter, COMP
Signal, the signal is input to the NOR gate 11, and when both signals are "L", the external pin 12 is set to "H" to output a defective state. The same applies to the determination circuit 9. The discriminating circuit 8 and the discriminating circuit 9 constitute a defect discriminating means 16.

In the above configuration, as shown in the timing chart of FIG. 2, the signal ▼ is lowered to take in the row address, and the signal ▼ is dropped to take in the column address, the word line WL ₁ is selected and the high level is selected. is activated, then the LE signal to the sense amplifier 1b rises, appear data of the memory cell 3a is in the bit line BL _1, the bit lines BL _1, ▲ ▼ information malfunction determination means 16
Amplified by

After the level of the bit line BL ₁ , ▲ ▼ changes, a reset signal is applied to the gates of the MOS transistors QP ₁ , QP ₂ as a pre-process for detecting a defect,
NP ₁ and NP ₂ are reset to a low level (the potential of the first power supply) Vss (that is, maintained in an initial state in advance). After that, the COMP signal rises and waits for failure determination.

Here, the selected memory cell 3a is the transistor 20a
And is constituted by a capacitor cell 20b, if when a defect resistor R ₁ so as to short-circuit to the ground potential with a value to the bit lines BL ₁ was present, of the bit lines BL ₁ final level high ( high potential) does not become Vcc or low level (power failure position) Vss, a current flows through the defect resistor R ₁ between the sense amplifier 1b and the ground potential, an intermediate level. In this example, the capacitor cell 20b is maintained in the data of a high level Vcc, because of the defective resistance R ₁ when a high level Vcc is going to leave the the bit lines BL _1, the bit lines BL ₁ intermediate level Vx, and the ▲ ▼ signal becomes "H", Vx becomes level enters the node N _C2 of the capacitor cells 20b at the time the word line WL ₁ is reset. At this time, assuming that the threshold level of the MOS transistor 6b is V _THP , the MOS transistor 6b is turned on if the relationship of Vcc−Vx> | V _THP | is satisfied.
Next node NP ₁ is charged up to a high level (potential of the second power supply). Thus, the level of the node NP ₁ is in the determination circuit 8 is supplied to be inverted by the inverter 10 ( "L" level so that) the NOR gate 11, the external pin 12 is made "H" level and the determination of the defective . This is taken out as a test result. With the defect is detected in the bit lines BL ₁ by the above process.

Similarly, the other bit lines ▲ ▼, ▲ ▼
Writing "1" to be the memory cells connected thereto, it can be detected defective by checking the potential of the node NP _2.

If such a detection method is used, even if the bit line is at an intermediate level, a defect can be detected only by judging the potentials of the nodes NP ₁ and NP _{2 in} a binary manner. , for example, writing a "1" in a row on the word line WL _1, is the effect that thereafter can be reliably determined in a short time failure detection cycle is obtained. Conventionally, data is read out for all memory cells and a test is performed. However, in this embodiment, one detection cycle is required for each bit line, and the test time is extremely short.

Above, but is poor in the case where the potential of the bit line attached defect resistor R ₁ to the bit line becomes the intermediate level and lower than a normal value, conversely, through the impedance with the bit line to this In the case where the power supply is short-circuited with the high-level Vcc power supply, the failure detection can be realized by the configuration shown in FIG. That is, in FIG. 3, a part of the configuration of the potential detecting means 20 is different from that of FIG.
▲ ▼, ▲ ▼ and node NP ₁ and bit line B
MOS transistors 21a to 21c and 22a to 22c constituting a first transistor provided between L ₀ , BL ₁ , BL ₂ and node NP ₂
Are configured as an N-channel type, and the others are the same as those in FIG.

Now, suppose that the value on the bit line BL ₁ is high level Vcc
If there is a defect resistance R ₂ that shorts with the power supply of
For example, when reading data “0”, the bit line BL ₁
The final level of not low, a high level current flows in the bit line BL ₁ through the defect resistor R ₂ from a power source of high level Vcc. Therefore, the MOS transistor 21b is turned on
And node NP ₁ and becomes the high level (potential of the second power supply). As a result, defect detection can be performed as in the case of FIG.

〔The invention's effect〕

According to the present invention, a functional test can be performed at a low cost and in a short time with a simple test pattern even when a potential at the time of selection is an intermediate level due to a defective bit line.

BRIEF DESCRIPTION OF THE DRAWINGS 1-3 Figure is a diagram showing an embodiment of a semiconductor memory device according to the present invention, FIG. 1 is a configuration diagram of a case of detecting the defect resistance R _1, FIG. 2 the timing chart thereof, FIG. 3 is a configuration diagram of a case of detecting the defect resistance R _2, FIG. 4 is a timing chart for performing a functional test for a conventional DRAM. 1a, 1b: Sense amplifier, 2a to 2d, 3a, 3b: Memory cell, 4a: Transfer gate MOS transistor, 4b: Capacitor cell, 5, 20: Potential detecting means, 6a to 6c, 7a to 7c , 21a to 21c, 22a to 22c ... MOS transistor, 8, 9 ... discriminating circuit, 10, 13 ... inverter, 11, 14 ... NOR gate, 12, 15 ... external pin, 16 ... defect discriminating means, WL ₁ , WL ₂ … word line, BL _{0 to} BL ₂ , ▲ ▼ to ▲ ▼… bit line.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G11C 29/00 G01R 31/28 G11C 11/401

Claims (1)

(57) [Claims] A potential detecting means for detecting a potential of a bit line; and a failure determining means for determining a failure of the bit line based on an output of the potential detecting means. And a first transistor, wherein the detection node is connected to a first power supply via a second transistor, a drain of the first transistor is connected to a second power supply, and the first transistor Is connected to the detection node. The gate of the first transistor is connected to the bit line. If the bit line is defective, the first transistor is turned on and the detection node is turned on. The potential of the bit line is raised to the potential of the second power supply, and the failure determination means determines the failure of the bit line.