JPH0287662A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0287662A
JPH0287662A JP24017388A JP24017388A JPH0287662A JP H0287662 A JPH0287662 A JP H0287662A JP 24017388 A JP24017388 A JP 24017388A JP 24017388 A JP24017388 A JP 24017388A JP H0287662 A JPH0287662 A JP H0287662A
Authority
JP
Japan
Prior art keywords
layer
gate
resistance
value
polycrystal silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24017388A
Other languages
Japanese (ja)
Other versions
JP2710356B2 (en
Inventor
Takayoshi Fujishiro
藤白　孝善
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP63240173A priority Critical patent/JP2710356B2/en
Publication of JPH0287662A publication Critical patent/JPH0287662A/en
Application granted granted Critical
Publication of JP2710356B2 publication Critical patent/JP2710356B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0802—Resistors only

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To correct the value of resistance to a desired value even though the scattering of manufacturing appears or its value of resistance changes after elements concerned are manufactured by installing a MOS transistor which has a resistance layer as source and drain regions together with the resistance layer which is formed in a semiconductor substrate. CONSTITUTION:A polycrystal silicon gate is formed through an insulating oxide layer 7 on a part of the surface of a resistance layer 3. A conductor layer 5 is in contact with the polycrystal silicon gate 4 through a contact hole 6 which penetrates into an insulator layer 8. Then a MOS transistor is formed in such a way that parts of the polycrystal silicon gate have the resistance layer at its both ends as source and drain regions and further, a surface part of the substrate located at a lower part of the polycrystal silicon gate 4 acts as a channel part. When gate voltage that excludes carriers is impressed on this gate, a depletion layer 10 is formed below the gate and the value of resistance between conductor layers 1 and 1 increases. It voltage impressed on the gate is adjusted, the value of resistance undergoes a change according to increase and decrease of above voltage.

Description

【発明の詳細な説明】 ［産業上の利用分野１ 本発明は、半導体装置に関し、特に、拡散抵抗体層を具
備する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application 1] The present invention relates to a semiconductor device, and particularly to a semiconductor device including a diffused resistor layer.

［従来の技術］ 従来、この種半導体装置の抵抗体層は、単に不純物を拡
散することのみによって形成されてきたが、その−例を
第３図（ａｍ　　（ｂ）に示す。第３図（ａ＞は、従来
例の平面図であり、第３図（ｂ）は、そのＹ−Ｙ’線断
面図である。これらの図において、不純物拡散抵抗体層
３は、半導体基板９内に形成され、その両端には電極と
して、絶縁酸化物層７、絶縁物層８を貫通するコンタク
トホール２を介して抵抗体層３と接触する導体層１が形
成されている。[Prior Art] Conventionally, the resistor layer of this type of semiconductor device has been formed simply by diffusing impurities, an example of which is shown in FIG. a> is a plan view of the conventional example, and FIG. 3(b) is a cross-sectional view taken along the line Y-Y'. A conductor layer 1 is formed as an electrode at both ends of the resistor layer 3 to contact the resistor layer 3 via a contact hole 2 penetrating the insulating oxide layer 7 and the insulator layer 8 .

［発明が解決しようとする問題点］ 上述した従来の抵抗体層は、不純物の拡散乃至注入時に
のみ抵抗値の制御ができるものであるので、次のような
問題点を有する。[Problems to be Solved by the Invention] The conventional resistor layer described above has the following problems because the resistance value can be controlled only when impurities are diffused or implanted.

■製造工程中のばらつきにより設計値どおりの抵抗値の
ものが製造されないことがある。■Due to variations in the manufacturing process, products with resistance values as designed may not be manufactured.

■製造後、そのデバイスの使用環境、特に、環境温度に
より、抵抗値が大きくずれる。■After manufacturing, the resistance value varies greatly depending on the environment in which the device is used, especially the environmental temperature.

■経年変化により、抵抗値が変わる。■Resistance value changes due to aging.

［問題点を解決するための手段］ 本発明の半導体装置は、半導体基板内に形成された不純
物拡散抵抗体層とその両端に接続されたコ一対の電極と
を具備しており、前記１対の電極間には、更に、前記不
純物拡散抵抗体層の少なくとも一部をそのソース・ドレ
イン領域とするＭＯＳトランジスタが接続されたもので
ある。[Means for Solving the Problems] A semiconductor device of the present invention includes an impurity diffused resistor layer formed in a semiconductor substrate and a pair of electrodes connected to both ends of the impurity diffused resistor layer. Furthermore, a MOS transistor having at least a portion of the impurity diffused resistor layer as its source/drain region is connected between the electrodes.

［実施例］ 次に、図面を参照して、本発明の実施例について説明す
る。[Example] Next, an example of the present invention will be described with reference to the drawings.

第１図（ａ＞は、本発明の一実施例の平面図であり、第
１図（ｂ）は、そのｘ−ｘ’線断面図である。これらの
図において、半導体基板９内には不純物拡散抵抗体Ｎ３
が形成されており、そして半導体基板９の表面は、絶縁
酸化物層７と絶縁物層８に覆われている。絶縁酸化物層
７は、不純物拡散抵抗体層３の表面上でその膜厚がＪく
なされている。不純物拡散抵抗体層３の両端には、その
電極となる導体層１が形成されており、そして、導体層
１は絶縁酸化物層７および絶縁物層８を貫通するコンタ
クトホール２を介して、不純物拡散抵抗体層３と接触し
ている。FIG. 1(a) is a plan view of one embodiment of the present invention, and FIG. 1(b) is a cross-sectional view taken along the line xx'. Impurity diffused resistor N3
is formed, and the surface of the semiconductor substrate 9 is covered with an insulating oxide layer 7 and an insulating layer 8. The insulating oxide layer 7 has a thickness of J on the surface of the impurity diffused resistor layer 3. A conductor layer 1 serving as an electrode is formed at both ends of the impurity diffused resistor layer 3, and the conductor layer 1 is connected to the conductor layer 1 through a contact hole 2 penetrating the insulating oxide layer 7 and the insulator layer 8. It is in contact with the impurity diffused resistor layer 3.

抵抗体層３の一部表面上には、絶縁酸化物層７を介して
、多結晶シリコンゲートが形成されている。この多結晶
シリコンゲート４には、絶縁物層８を貫通するコンタク
トホール６を介して導体層５が接触している。A polycrystalline silicon gate is formed on a part of the surface of the resistor layer 3 with an insulating oxide layer 7 interposed therebetween. A conductor layer 5 is in contact with this polycrystalline silicon gate 4 via a contact hole 6 penetrating an insulator layer 8 .

而して、この装置において多結晶シリコンゲート部分に
おいては、その両端の抵抗体層をソース・ドレイン領域
とし、多結晶シリコンゲート４の下部の基板表面部分を
チャネル部とするＭ　ＯＳ　ｈランジスタが形成されて
いる。そして、このゲートに、キャリアを排斥するゲー
ト電圧が印加されると、ゲート下は空乏層１０が形成さ
れて、導体層１．１間の抵抗値は増大する。ここで、ゲ
ートに印加する電圧を加減するならば、それに応じて抵
抗値も増減する。従って、ゲート電圧を調整することに
より、抵抗値を所望の値とすることができる。In this device, in the polycrystalline silicon gate portion, an MOS h transistor is formed in which the resistor layers at both ends serve as source/drain regions, and the substrate surface portion below the polycrystalline silicon gate 4 serves as a channel portion. has been done. When a gate voltage that excludes carriers is applied to this gate, a depletion layer 10 is formed under the gate, and the resistance value between the conductor layers 1.1 increases. Here, if the voltage applied to the gate is adjusted, the resistance value will also increase or decrease accordingly. Therefore, by adjusting the gate voltage, the resistance value can be set to a desired value.

次に、第２図（ａ＞、（ｂ）を参照して本発明の他の実
施例について説明する。第２図（ａ＞、（ｂ）は、それ
ぞれ、この実施例の平面図と断面図であって、第１図（
ａ＞、（ｂ）のものと同一の部分には同一の番号が付さ
れているので詳細な説明は省略するが、この実施例にお
いては、多結晶シリコンゲート４が、不純物拡散抵抗体
層４の全幅にわたって形成されている。このようにすれ
ば、抵抗値を大きく変化させることができる。Next, another embodiment of the present invention will be described with reference to FIGS. 2(a> and 2b). FIGS. Figure 1 (
Since the same parts as in a> and (b) are given the same numbers, a detailed explanation will be omitted, but in this embodiment, the polycrystalline silicon gate 4 is It is formed over the entire width of the In this way, the resistance value can be greatly changed.

以上の実施例では、ＭＯＳ）ランジスタのソース・ドレ
イン領域とチャネル部とが同一導電型同一不純物濃度の
ものであったが、この構成のものは、チャネルドーピン
グのような特別の工程を必要としないので、製法上有利
である。しかしながら、本発明は、これに限定されるも
のではない。In the above embodiments, the source/drain region and the channel part of the MOS transistor were of the same conductivity type and the same impurity concentration, but this configuration does not require any special process such as channel doping. Therefore, it is advantageous in terms of manufacturing method. However, the present invention is not limited thereto.

例えば、抵抗体層であるソース・ドレイン領域がＮ型領
域である場合に、チャネル部は、Ｎ−型領域、Ｐ−型領
域あるいはＰ型領域の何れであってもよい。換言すれば
、本発明で用いるＭｏＳトランジスタは、エンハンスメ
ント型、デプリーション型のいずれでもよいということ
である。また、本発明においては、ＭｏＳトランジスタ
のゲートに、多数キャリアに対して蓄積モードあるいは
排斥モード（反転モード）となる何れの電圧を印加して
もよい。要は、チャネル部の抵抗を有効に制御して、適
切な抵抗値のものが得られればよいのである。For example, when the source/drain region of the resistor layer is an N-type region, the channel portion may be any of an N-type region, a P-type region, or a P-type region. In other words, the MoS transistor used in the present invention may be either an enhancement type or a depletion type. Further, in the present invention, any voltage may be applied to the gate of the MoS transistor to set the majority carrier in an accumulation mode or an exclusion mode (inversion mode). The point is that the resistance of the channel portion can be effectively controlled to obtain an appropriate resistance value.

本発明の多結晶シリコンゲートは、標準的Ｍ○Ｓ■Ｃの
製造工程中において形成することができるので、本発明
の抵抗器は格別の工程を付加することなく、製造するこ
とができる。Since the polycrystalline silicon gate of the present invention can be formed during standard M*S*C manufacturing processes, the resistor of the present invention can be manufactured without additional steps.

［発明の効果〕 以上説明したように、本発明は、半導体基板内に形成さ
れた抵抗体層とともにこの層をソースドレイン領域とす
るＭＯＳ）ランジスタを設けたものであるから、抵抗体
層を形成する不純物ドーピング工程において、製造上の
ばらつきが発生しても、あるいは製造後に抵抗値が変化
しても、ＭＯＳトランジスタに適切なゲート電圧を印加
することによって、抵抗値を所望の値に補正することが
できる。[Effects of the Invention] As explained above, the present invention provides a resistor layer formed in a semiconductor substrate as well as a MOS transistor that uses this layer as a source/drain region. Even if manufacturing variations occur during the impurity doping process, or even if the resistance value changes after manufacturing, the resistance value can be corrected to the desired value by applying an appropriate gate voltage to the MOS transistor. Can be done.

【図面の簡単な説明】[Brief explanation of the drawing]

第１　ＵＡ　（ａ　）は、本発明の一実施例の平面図、
第１図（ｂ）は、そのｘ−ｘ’線断面図、第２図（ａ＞
は、本発明の他の実施例の平面図、第２図（ｂ）は、そ
の断面図、第３図＜ａ）は、従来例の平面図、第３図（
ｂ）は、そのＹ−Ｙ’線断面図である。 １．５・・・導体層、　２．６・・コンタクトホール３
・・・不純物拡散抵抗体層、　４・・・多結晶シリコン
ゲート、　７・・・絶縁酸化物層、　８・・絶縁物層、
　９・・・半導体基板、　１０・・・空乏層。The first UA (a) is a plan view of an embodiment of the present invention,
Fig. 1(b) is a sectional view taken along the line xx', and Fig. 2(a>
is a plan view of another embodiment of the present invention, FIG. 2(b) is a sectional view thereof, FIG. 3<a) is a plan view of a conventional example, and FIG.
b) is a sectional view taken along the Y-Y' line. 1.5...Conductor layer, 2.6...Contact hole 3
... Impurity diffused resistor layer, 4... Polycrystalline silicon gate, 7... Insulating oxide layer, 8... Insulator layer,
9... Semiconductor substrate, 10... Depletion layer.

Claims (1)

【特許請求の範囲】[Claims] 半導体基板と、該半導体基板内に形成された不純物拡散
抵抗体層と、該不純物拡散抵抗体層に接続された１対の
電極とを具えた半導体装置において、前記１対の電極の
間には、前記不純物拡散抵抗体層の少なくとも一部をそ
のソース・ドレイン領域とするＭＯＳトランジスタが接
続されていることを特徴とする半導体装置。In a semiconductor device including a semiconductor substrate, an impurity diffused resistor layer formed in the semiconductor substrate, and a pair of electrodes connected to the impurity diffused resistor layer, there is a gap between the pair of electrodes. . A semiconductor device, further comprising a MOS transistor connected thereto, the source/drain region of which is at least a portion of the impurity diffused resistor layer.
JP63240173A 1988-09-26 1988-09-26 Semiconductor device Expired - Lifetime JP2710356B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63240173A JP2710356B2 (en) 1988-09-26 1988-09-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63240173A JP2710356B2 (en) 1988-09-26 1988-09-26 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH0287662A true JPH0287662A (en) 1990-03-28
JP2710356B2 JP2710356B2 (en) 1998-02-10

Family

ID=17055562

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63240173A Expired - Lifetime JP2710356B2 (en) 1988-09-26 1988-09-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2710356B2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56167360A (en) * 1980-05-26 1981-12-23 Mitsubishi Electric Corp Diffused resistance element in semiconductor device
JPS60244058A (en) * 1984-05-18 1985-12-03 Nec Ic Microcomput Syst Ltd Semiconductor integrated circuit device
JPS6316654A (en) * 1986-07-08 1988-01-23 Nec Corp Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56167360A (en) * 1980-05-26 1981-12-23 Mitsubishi Electric Corp Diffused resistance element in semiconductor device
JPS60244058A (en) * 1984-05-18 1985-12-03 Nec Ic Microcomput Syst Ltd Semiconductor integrated circuit device
JPS6316654A (en) * 1986-07-08 1988-01-23 Nec Corp Semiconductor device

Also Published As

Publication number Publication date
JP2710356B2 (en) 1998-02-10

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