GB1586423A - Field-effect transistors - Google Patents
Field-effect transistors Download PDFInfo
- Publication number
- GB1586423A GB1586423A GB19497/78A GB1949778A GB1586423A GB 1586423 A GB1586423 A GB 1586423A GB 19497/78 A GB19497/78 A GB 19497/78A GB 1949778 A GB1949778 A GB 1949778A GB 1586423 A GB1586423 A GB 1586423A
- Authority
- GB
- United Kingdom
- Prior art keywords
- gate electrode
- field
- gap
- effect transistor
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000005669 field effect Effects 0.000 title claims description 37
- 239000004065 semiconductor Substances 0.000 claims description 35
- 238000000034 method Methods 0.000 claims description 14
- 239000011248 coating agent Substances 0.000 claims description 13
- 238000000576 coating method Methods 0.000 claims description 13
- 150000002500 ions Chemical class 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 9
- 239000012799 electrically-conductive coating Substances 0.000 claims description 8
- 239000002800 charge carrier Substances 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 5
- 239000004411 aluminium Substances 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 230000001133 acceleration Effects 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 238000007493 shaping process Methods 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Description
(54) IMPROVEMENTS IN OR RELATING TO FIELD-EFFECT TRANSISTORS
(71) We, SIEMENS
AKTIENGESELLSCHAFT, a German
Company of Berlin and Munich, German
Federal Republic, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed to be particularly described in and by the following state ment:- The present invention relates to fieldeffect transistors having an extremely short channel length of the kind comprising a doped semiconductor layer of one conductivity type having formed in the surface thereof oppositely doped source and drain zones of the other conductivity type, and a gate electrode separated from the semiconductor surface by an electrically insulating layer.
Transistors of this kind are described, for example, in an article in "IEEE Journal of
Solid-State Circuits", Vol. SC-10, No 5,
Oct. 1975, at pages 322-331. In order to produce a high punch-through voltage (i.e.
that value of the drain voltage at which the drain-side depletion zone reaches the source zone) and in order to simultaneously prevent the drain voltage from appreciably influencing the internal resistance of the transistor impedance, the transistors described in this publication are designed as so-called "DMOS field-effect transistors" by which is meant an MOS-transistor produced by using a double-diffusion technique, in which the source zones and drain zones are diffused into the surface of a doped semiconductor layer at a normal spacing from one another, but this diffusion step is preceded by another diffusion step in which a tub-shaped diffusion zone is formed in the semi-conductor surface, having the same conductivity type as the semiconductor layer but which is more highly doped, and into which the source zone is subsequently diffused.
By means of this DMOS-technique, a transistor is formed, having a channel which, for the main part, runs between the edge of the tub-shaped diffused zone and the edge of the drain zone, only a very small part thereof lying between the edge of the tub-shaped diffused zone and the edge of the source zone within the tub-shaped zpne.
This latter part of the channel determines the effective channel length of the transistor within which the charge carrier transport is controlled by means of the gate electrode insulated from the semiconductor surface and to which a control voltage is supplied, whilst the punch-through voltage has a value similar to those occurring with MOS fieldeffect transistors having a channel length equal to the distance between the source and drain zones.
However, field-effect transistors produced using the DMOS technique have the disadvantage that the effective channel length is dependent upon the course of the double-diffusion process. Since a plurality of similar transistors, usually arranged on a common substrate, are generally simultaneously produced by this process, the effective channel lengths and the saturation voltages of all these transistors (in the case of the saturation voltage assuming the same gate voltages) are either identical with one another or, at least, are related to one another in a process-dependent way.
It is an object of the present invention to provide a field-effect transistor of the kind initially referred to having an extremely short channel length, wherein the disadvantages of the known transistors referred to above do not occur when a plurality of such transistors are simultaneously produced.
According to the invention, there is provided a field-effect transistor having an extremely short channel length, comprising a doped semiconductor layer of one conductivity type having spaced source and drain zones of the opposite conductivity type formed in the surface thereof, a first gate electrode separated from the surface of said semiconductor layer by a first electrically insulating layer and divided into two parts by a gap extending transversely to the direction of movement of charge carriers between said source and drain zones in use, the width of said gap determining the effective channel length of the transistor, and a second gate electrode arranged above said gap and separated from the two parts of said first gate electrode by a second electrically insulating layer, the two parts of said first gate electrode each being provided with a respective terminal for connection to a respective voltage source, and said second control gate being provided with a terminal for connection to a control voltage source.
The field-effect transistors of the invention have effective channel lengths which are determined only by the geometric dimensions of areas which can be individually defined, e.g. by etching, for each individual one of a plurality of transistors subjected to a common diffusion process.
Moreover, the saturation voltages of the individual field-effect transistors at the drain electrodes can be selected or adjusted in a simple manner.
The invention will now be further described with reference to the drawing, which is a schematic side-sectional view of one embodiment thereof.
Referring to the drawing, a field-effect transistor has a channel zone which is located at the surface of a p-doped semiconductor layer 1 consisting, for example, of silicon, between an n±doped source zone 2 and an n±doped drain zone 3. The semiconductor surface is covered with a first electrically insulating layer 4, which may consist, for example, of SiO2, above which is arranged a first gate electrode consisting of two parts Saand 5b. The two parts of the gate electrode are separated from one another by a narrow gap 6 which runs substantially transversely to the direction of movement of charge carriers transported between the source and drain zones. Above the first gate electrode 5a, 5b, there is arranged a second insulating layer 7 which also covers this electrode in the region of the electrode faces which adjoin the gap 6. A second gate electrode 8 is arranged above the gap area and is so shaped that it projects into the gap 6; this electrode 8 is provided with a terminal 9 which in use is connected to a source of a controlling gate voltage Uc2. As schematically indicated in the drawing, the electrode parts 5a and 5b are provided with respective terminals 10 and 11 which are connected in use to bias voltages Uc,. and UGlh The source zone 2 is connected via a terminal 12 to a reference potential, and the drain zone is connected via a terminal 13 to a drain voltage UD. The semiconductor layer 1 is connected via a terminal la to a substrate potential Usub.
When positive bias voltages UGla and
UGlb are supplied to the parts 5a and Sb of the first gate electrode and a positive drain voltage is connected to the terminal 13, the movement of charge carriers between the source zone 2 and the drain zone 3 is controlled in dependence upon a generally positive gate voltage UG2 which is applied to the second gate electrode 9. Control occurs within the effective channel zone 14, the length of which corresponds approximately to the width of the gap 6. In this case, the electrical behaviour corresponds to that of a field-effect transistor of the enhancement type. The gap width can be geometrically established, for example, by means of the dimensions of a mask window used in producing the gap by etching. When a plurality of such transistors are produced using common production steps, it is therefore possible to to produce different gap widths and thus effective channel lengths for the individual transistors. The width of the gap 6 and thus the effective channel length 14 of the individual transistors can, for example, by 1 llm or even less.
By suitable selection of the bias voltage
UGla it is possible to simply adjust the saturation voltage UDs at the drain terminal 13 independently of the controlling gate voltage UG2. Expediently, the bias voltage UBlb applied to the electrode component 5b is selected to be greater than UGla in order to achieve a good controllability of the channel control voltage UG2. It is particularly advantageous if the bias voltage UGla iS variable, in which case the saturation voltage of the transistor can be adapted to the particular requirements in operation in each individual case.
It is not essential for the semiconductor layer 1 to be p-doped, as described above; it may be p-doped or doped, in which case the surface doping of the channel zone 14 should be simultaneously raised to a pdoping value, for example, by the local implantation of acceptor ions. This serves to reduce the interference capacitances at the p-n juntions of the source and drain zones 2 and 3 respectively, and to increase the punch-through voltages at these junctions without thereby altering the other electrical properties of the transistor. In the case of p-doping of the semiconductor layer 1, it is also expedient to raise the surface doping of the channel zone 14 to a somewhat higher value in order to achieve a reliable control of the channel control by means of the control voltage UG2.
The field-effect transistor of the invention can be expediently produced by first ap plying a first insulating layer 4 to cover the surface of the semiconductor layer 1. A first electrically conductive coating is then applied to this insulating layer. The parts of the divided first gate electrode 5a and Sb are then formed from this conductive coating by producing the gap 6, by selectively etching away a narrow strip of this coating and simultaneously producing the desired outlines of the electrodes Sa and Sb by simultaneously etching away further peripheral parts of this coating. Finally, after the application of a further insulating layer 7 which covers the first gate electrode Sa, Sb in the vicinity of the gap 6, there is arranged on this layer 7 a second electrically conductive coating above the gap 6 from which the second gate electrode 8 is formed by known process steps, for example, photolithographically. The shaping of the parts of the first gate electrode 5a and Sb means that these parts can then be used as masks in a subsequent implantation of donor ions to form the source and drain zones 2 and 3 respectively.
In order to raise the surface level of the doping in the channel zone 14, preferably after the formation of the gap 6 in the first conductive coating, an ion implantation using acceptor ions is carried out using an ion acceleration which is such that the ions do not penetrate through the first gate electrode Sa, Sb, which thus serves as a doping mask.
The semiconductor dopings specified in the particular exemplary embodiment described above can, of course, be modified by reversing the conductivity types of the individual semiconductor zones, in which case operating voltages of the opposite polarity must be used. The first gate electrode Sa, Sb and/or the second gate electrode 8 may consist of heavily doped semiconductor material, in particularly polysilicon, or may consist of a metal, in particular aluminium.
WHAT WE CLAIM IS:
1. A field-effect transistor having an extremely short channel length, comprising a doped semiconductor layer of one conductivity type having spaced source and drain zones of the opposite conductivity type formed in the surface thereof, a first gate electrode separated from the surface of said semiconductor layer by a first electrically insulating layer and divided into two parts by a gap extending transversely to the direction of movement of charge carriers between said source and drain zones in use, the width of said gap determining the effective channel length of the transistor, and a second gate electrode arranged above said gap and separated from the two parts of said first gate electrode by a second electrically insulating layer, the two parts of said first gate electrode each being provided with a respective terminal for connection to a respective voltage source, and said second control gate being provided with a terminal for connection to a control voltage source.
2. A field-effect transistor as claimed in
Claim 1, wherein said second gate electrode is shaped to project into said gap.
3. A field-effect transistor as claimed in
Claim 1 or Claim 2, wherein in use an adjustable bias voltage is supplied to the part of said first gate electrode adjacent said drain zone.
4. A field-effect transistor as claimed in any one of Claims 1 to 3, wherein in use a bias voltage is supplied to the part of said first gauge electrode adjacent to said source zone which is greater than a bias voltage supplied to the part of said first gate electrode adjacent to said drain zone.
5. A field-effect transistor as claimed in any one of the preceding Claims, wherein the semiconductor layer is more highly doped in a strip-shaped surface zone lying beneath said gap than in the remainder of the layer.
6. A field-effect transistor as claimed in any one of the preceding Claims, wherein said first and/or said second gate electrode is or are made of highly doped semiconductor material.
7. A field-effect transistor as claimed in
Claim 6, wherein said highly doped semiconductor material is highly-doped polysilicon.
8. A field-effect transistor as claimed in any one of Claims 1 to 5, wherein said first and/or said second gate electrode is of metal.
9. A field-effect transistor as claimed in
Claim 8, wherein said metal is aluminium.
10. A field-effect transistor substantially as hereinbefore described with reference to and as illustrated in the drawing.
11. A process for the production of a field-effect transistor as claimed in Claim 1, comprising the steps of applying a first electrically insulating layer to cover the surface of said doped semiconductor layer; arranging a first electrically conductive coating on said first insulating layer; forming the two parts of said first gate electrode from said conductive coating by selective etching; applying a second electrically insulating layer to cover said first gate electrode; applying a second electrically conductive coating to said second insulating layer above said gap; forming said second gate electrode from said second conductive coating; and forming said source and drain zones by ion implantation using the two parts of said first gate electrode as an implantation mask.
12. A process as claimed in Claim 8, wherein the surface doping of the semiconductor layer within a strip-shaped zone lying below said gap is increased by an ion
**WARNING** end of DESC field may overlap start of CLMS **.
Claims (14)
1. A field-effect transistor having an extremely short channel length, comprising a doped semiconductor layer of one conductivity type having spaced source and drain zones of the opposite conductivity type formed in the surface thereof, a first gate electrode separated from the surface of said semiconductor layer by a first electrically insulating layer and divided into two parts by a gap extending transversely to the direction of movement of charge carriers between said source and drain zones in use, the width of said gap determining the effective channel length of the transistor, and a second gate electrode arranged above said gap and separated from the two parts of said first gate electrode by a second electrically insulating layer, the two parts of said first gate electrode each being provided with a respective terminal for connection to a respective voltage source, and said second control gate being provided with a terminal for connection to a control voltage source.
2. A field-effect transistor as claimed in
Claim 1, wherein said second gate electrode is shaped to project into said gap.
3. A field-effect transistor as claimed in
Claim 1 or Claim 2, wherein in use an adjustable bias voltage is supplied to the part of said first gate electrode adjacent said drain zone.
4. A field-effect transistor as claimed in any one of Claims 1 to 3, wherein in use a bias voltage is supplied to the part of said first gauge electrode adjacent to said source zone which is greater than a bias voltage supplied to the part of said first gate electrode adjacent to said drain zone.
5. A field-effect transistor as claimed in any one of the preceding Claims, wherein the semiconductor layer is more highly doped in a strip-shaped surface zone lying beneath said gap than in the remainder of the layer.
6. A field-effect transistor as claimed in any one of the preceding Claims, wherein said first and/or said second gate electrode is or are made of highly doped semiconductor material.
7. A field-effect transistor as claimed in
Claim 6, wherein said highly doped semiconductor material is highly-doped polysilicon.
8. A field-effect transistor as claimed in any one of Claims 1 to 5, wherein said first and/or said second gate electrode is of metal.
9. A field-effect transistor as claimed in
Claim 8, wherein said metal is aluminium.
10. A field-effect transistor substantially as hereinbefore described with reference to and as illustrated in the drawing.
11. A process for the production of a field-effect transistor as claimed in Claim 1, comprising the steps of applying a first electrically insulating layer to cover the surface of said doped semiconductor layer; arranging a first electrically conductive coating on said first insulating layer; forming the two parts of said first gate electrode from said conductive coating by selective etching; applying a second electrically insulating layer to cover said first gate electrode; applying a second electrically conductive coating to said second insulating layer above said gap; forming said second gate electrode from said second conductive coating; and forming said source and drain zones by ion implantation using the two parts of said first gate electrode as an implantation mask.
12. A process as claimed in Claim 8, wherein the surface doping of the semiconductor layer within a strip-shaped zone lying below said gap is increased by an ion
implantation step carried out after the formation of said gap by selective etching, using an ion acceleration such that said first conductive coating serves as an implantation mask.
13. A process for the production of a field-effect transistor as claimed in Claim 1, substantially as hereinbefore described with reference to the drawing.
14. A field-effect transistor produced by a method as claimed in any one of Claims 11 to 13.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19772729658 DE2729658A1 (en) | 1977-06-30 | 1977-06-30 | FIELD EFFECT TRANSISTOR WITH EXTREMELY SHORT CHANNEL LENGTH |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1586423A true GB1586423A (en) | 1981-03-18 |
Family
ID=6012852
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB19497/78A Expired GB1586423A (en) | 1977-06-30 | 1978-05-15 | Field-effect transistors |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS5414175A (en) |
| DE (1) | DE2729658A1 (en) |
| FR (1) | FR2396416A1 (en) |
| GB (1) | GB1586423A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4587709A (en) * | 1983-06-06 | 1986-05-13 | International Business Machines Corporation | Method of making short channel IGFET |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4319263A (en) * | 1978-05-18 | 1982-03-09 | Texas Instruments Incorporated | Double level polysilicon series transistor devices |
| JPS57204172A (en) * | 1981-06-08 | 1982-12-14 | Ibm | Field effect transistor |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3355598A (en) * | 1964-11-25 | 1967-11-28 | Rca Corp | Integrated logic arrays employing insulated-gate field-effect devices having a common source region and shared gates |
| GB1139170A (en) * | 1965-12-22 | 1969-01-08 | Mullard Ltd | Thin film transistors |
| FR1511783A (en) * | 1966-04-15 | 1968-02-02 | Philco Ford Corp | Metal-insulator-semiconductor transistor, comprising multiple control electrodes |
-
1977
- 1977-06-30 DE DE19772729658 patent/DE2729658A1/en not_active Ceased
-
1978
- 1978-05-15 GB GB19497/78A patent/GB1586423A/en not_active Expired
- 1978-06-26 FR FR7819007A patent/FR2396416A1/en active Granted
- 1978-06-30 JP JP8046178A patent/JPS5414175A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4587709A (en) * | 1983-06-06 | 1986-05-13 | International Business Machines Corporation | Method of making short channel IGFET |
Also Published As
| Publication number | Publication date |
|---|---|
| DE2729658A1 (en) | 1979-01-11 |
| FR2396416A1 (en) | 1979-01-26 |
| JPS5414175A (en) | 1979-02-02 |
| FR2396416B1 (en) | 1982-12-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed | ||
| PCNP | Patent ceased through non-payment of renewal fee |