JPH0284441U

JPH0284441U -

Info

Publication number: JPH0284441U
Application number: JP16420188U
Authority: JP
Priority date: 1988-12-19
Filing date: 1988-12-19
Publication date: 1990-06-29

Description

[Brief explanation of drawings]

第１図は、本考案の一実施例を示すブロツク図
、第２図、第３図は本考案の説明に供するタイミ
ングチヤート図、及び周波数特性図。１……位相比較部、２……スイツチ、３……ロ
ーパスフイルタ、４……電圧制御発振器、５……
４進カウンタ、６，９……ＯＲ回路、７……Ｄ型
フリツプフロツプ回路、８……遅延回路、１０…
…形成クロツク信号出力端子、１１……外部クロ
ツク信号入力端子、１２……パルス発生回路、１
３……鋸波発生回路、１４……サンプルホールド
回路。 FIG. 1 is a block diagram showing one embodiment of the present invention, and FIGS. 2 and 3 are timing charts and frequency characteristic diagrams for explaining the present invention. 1... Phase comparator, 2... Switch, 3... Low pass filter, 4... Voltage controlled oscillator, 5...
Quaternary counter, 6, 9...OR circuit, 7...D flip-flop circuit, 8...Delay circuit, 10...
... Formation clock signal output terminal, 11 ... External clock signal input terminal, 12 ... Pulse generation circuit, 1
3... sawtooth wave generation circuit, 14... sample hold circuit.

補正平１．９．２０実用新案登録請求の範囲を次のように補正する
。Amendment 9/20/1999 The scope of claims for utility model registration is amended as follows.

【実用新案登録請求の範囲】外部クロツク信号を入力し、これに同期する形
成クロツク信号を形成するクロツク同期回路であ
り、前記形成クロツク信号に同期して充放電を繰り
返す鋸波発生回路と前記外部クロツク信号に同期
して前記鋸波を逐次サンプルホールドしたＳＨ信
号を出力するサンプルホールド回路からなる位相
比較手段と、前記ＳＨ信号を入力し、応答速度の異なる２種
類の制御信号を択一的に出力する制御信号出力手
段と、前記２種類の制御信号のうち、応答速度の速い
第１の制御信号、又は応答速度の遅い第２の制御
信号のレベルに応答する周波数を有する前記形成
クロツク信号を出力する形成クロツク信号出力手
段と、前記外部クロツク信号と前記形成クロツク信号
の位相関係を監視し、位相差が所定の範囲内に在
ることを示す第１の状態と該位相差が所定の範囲
外に在ることを示す第２の状態とからなる位相差
監視信号を出力する位相差監視手段と、前記位相差監視信号を入力し、該位相差監視信
号の前記第２の状態から前記第１の状態への変化
時のみ所定時間遅延した遅延信号を出力する信号
遅延手段とからなり、前記制御信号出力手段が前記遅延信号に基づい
て、少なくとも前記位相差監視信号が前記第２の
状態の間、前記第１の制御信号を出力するように
構成したことを特徴とするクロツク同期回路。 [Claims for Utility Model Registration] A clock synchronization circuit that inputs an external clock signal and forms a forming clock signal synchronized with the external clock signal, which comprises a sawtooth wave generating circuit that repeats charging and discharging in synchronization with the forming clock signal, and the external clock signal. phase comparison means consisting of a sample and hold circuit that outputs an SH signal obtained by sequentially sampling and holding the sawtooth wave in synchronization with a clock signal; a control signal output means for outputting the forming clock signal having a frequency responsive to a level of a first control signal having a faster response speed or a second control signal having a slower response speed among the two types of control signals; a forming clock signal output means for outputting a forming clock signal; and a first state in which the phase relationship between the external clock signal and the forming clock signal is monitored and the phase difference is within a predetermined range; a phase difference monitoring means for outputting a phase difference monitoring signal consisting of a second state indicating that the phase difference monitoring signal is outside; signal delay means for outputting a delayed signal delayed by a predetermined time only when the state changes to the second state; 2. A clock synchronization circuit, characterized in that said clock synchronization circuit is configured to output said first control signal during a period of time.

Claims

[Claims for Utility Model Registration] A clock synchronization circuit that inputs an external clock signal and forms a forming clock signal synchronized with the clock signal, comprising: phase comparison means consisting of a sawtooth wave generation circuit and a sample and hold circuit; and the external clock signal. and a phase difference monitoring means for monitoring the phase relationship between the formed clock signal and the formed clock signal, and outputting a phase difference monitoring signal indicating that the phase difference is outside a predetermined range; 1. A clock synchronization circuit comprising: response speed setting means for setting two types of response speeds of a forming clock signal to said external clock signal.