JPS62200823A - Detection circuit for frequency drift of phase locked oscillator - Google Patents

Abstract

PURPOSE:To detect accurately a frequency drift by constituting a detection circuit by a sample and holding circuit and a decoder decoding the internal state of an output side frequency divider provided with a phase locked oscillator. CONSTITUTION:The frequency drift detection circuit consists of a decoder 7 decoding the internal state of a frequency divider 5 and a sample and holding circuit 8 sampling and holding the decoder output by using a reference input signal. The sample and holding circuit 8 uses the reference input signal (a) so as to sample an output signal (c) of the decoder 7 and holds the state up to the next sample. Figure shows waveforms of each part in detecting a fre quency drift where the oscillated frequency of a voltage controlled oscillator 4 rises abnormally and the leading edge of the reference input signal (a) comes to a high level of the output (c). In this case, the output of the sample and holding circuit 8 outputs a high level, that is, an alarm and the frequency drift detection circuit indicates that the phase locked oscillator generates a frequency drift.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frequency drift detection circuit for a phase synchronized oscillator that operates in synchronization with the frequency of a reference signal.

[Conventional technology]

As a means for monitoring abnormal operation of the phase-locked oscillator, there is a method of providing a frequency drift detection circuit that monitors whether the phase-locked oscillator approaches the end of its lock range before it loses lock.

FIG. 4 shows a conventional frequency drift detection circuit, in which the portion surrounded by a broken line is the frequency drift detection circuit.

In the figure, 10 is an input terminal for the input signal d of the reference frequency, 11
1 is a phase comparator; 12 is a low-pass filter; 13 is a voltage-controlled oscillator; 14 is a frequency divider that divides the oscillation output signal of the voltage-controlled oscillator 13 to be equal to the frequency of the reference signal;
5 is an output terminal of the voltage controlled oscillator 13. Inside the broken line in FIG. 4, 16 and 18 are a time signal generation circuit, 17 and 19 are sample and hold circuits, 20 is an OR gate, and 21 is an output terminal of a frequency drift detection circuit.

Note that e is the output signal of the frequency divider 14, and f is the output signal of the phase comparator 11.
The output signals g and h are respectively from the time signal generation circuit 1.
6.18 output signal.

FIG. 5 shows operating waveforms of the phase synchronized oscillator shown in FIG. 4 when detecting a drift. In addition, the waveforms d, e, in FIGS. 5 and 6
f, g, h are the signals d, e, f, g, . . . in FIG. 4, respectively.
This is the waveform of h.

The time signal generation circuit 16 is triggered by the rising edge of the reference input signal d, and outputs a signal g whose pulse width T1 is determined by the constants of passive elements such as resistors and capacitors. The time signal generation circuit 18 is triggered by the rising edge of the frequency-divided output signal e of the frequency divider 14, and outputs a signal whose pulse width T2 is determined by the constant of the passive element, similar to the time signal generation circuit 16. The sample hold circuit 17 is the time signal generation circuit 1
The output signal g of the frequency divider 14 is sampled and held at the rising edge of the output signal e of the frequency divider 14. Also, sample hold circuit 1
Reference numeral 9 samples and holds the output signal of the time signal generating circuit 18 at the rising edge of the reference signal d.

When the phase synchronized oscillator operates normally, the sample and hold circuits 17 and 19
The outputs of both are low level, the output of the OR gate 20 which takes the logical sum is also low level, and the alarm output terminal 21 of this frequency drift detection circuit is low level, that is, normal.

The case in FIG. 6 shows a case where the oscillation frequency of the voltage controlled oscillator 13 has increased abnormally, and the rising edge of the output signal e of the frequency divider 14 approaches the rising edge of the reference signal d below Tl. It is something. In this case, the output of the sample hold circuit 17 becomes high level, and the flu output terminal 2
1 also becomes high level and generates an alarm.

When the oscillation frequency of the voltage controlled oscillator 13 falls abnormally, the sample hold circuit 19 side outputs a high level,
Generates an alarm. Here, T, , T2 are the values that determine the alarm generation threshold, and the voltage controlled oscillator 1
Since the control characteristics of No. 3 are linear, 'r, , T2 take the same value.

[Problem that the invention seeks to solve]

The conventional frequency drift detection circuit described above requires two sets of detection circuits and an OR gate in order to detect both an abnormal increase and an abnormal decrease in the oscillation frequency of the voltage controlled oscillator, and also requires two sets of detection circuits and an OR gate. The pulse width 71 + T2 is determined by the constants of the passive elements of the generation circuit 16.18,
Since a variable resistor or the like is also required to compensate for the deviation, this conventional circuit has the disadvantage that it cannot be manufactured at low cost.

An object of the present invention is to provide a frequency drift detection circuit with a simple configuration.

[Means for solving problems]

The frequency drift detection circuit for a phase-locked oscillator of the present invention includes:
It is comprised of a decoder that decodes the internal state of an output-side frequency divider included in a phase-locked oscillator, and a sample-and-hold circuit that samples the decoder output with a reference input signal to the phase-locked oscillator.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

Inside the broken line is the drift detection circuit of the phase-locked oscillator of this embodiment. The phase-locked oscillator includes a reference signal input terminal l, a phase comparator 2, a low-pass filter 3, and a voltage-controlled oscillator 4.
, a frequency divider 5, and an output terminal 6 of a phase-locked oscillator. The frequency drift detection circuit includes a decoder 7 that decodes the internal state of the frequency divider 5, and a sample-and-hold circuit 8 that uses the decoder output as a reference input signal.

In the figure, a is the reference input signal, b is the output signal of the frequency divider 5, and C
indicate the output signals of the decoder 7, respectively.

FIG. 2 shows operating waveforms when the phase synchronized oscillator shown in FIG. 1 is normal, and FIG. 3 shows operating waveforms when a frequency drift is detected.

In FIG. 1, a frequency divider 5 divides the frequency of the output signal of the voltage controlled oscillator 4 to be equal to the frequency of the reference input signal a, and sends the internal state to the decoder 7. When the frequency divider 5 is an N frequency divider, the decoder 7 determines that the state of the frequency divider is n.
1 in the range from l to n2 (0<nl <fi2<N)
, otherwise set to output 0.

The sample and hold circuit 8 samples the output signal C of the decoder 7 using the reference input signal a, and holds that state until the next sample. It is assumed that the phase synchronized oscillator is normal when the output of the sample and hold circuit 8Q, that is, the output of the output terminal 9 is O, and that it is abnormal when the output is 1.

FIG. 2 shows the waveforms of each part during normal operation, and the output signal C of the decoder 7 is obtained in response to the frequency divider output signal. Since the output signal C of the decoder 7 is sampled and held at the rising edge of the reference input signal a, in the case of FIG.
When the reference input signal a rises, the output signal C of the decoder 7
indicates a low level, the output terminal 9 outputs a low level, and the frequency drift detection circuit indicates normality.

FIG. 3(A) shows the waveforms of various parts when a frequency drift is detected when the oscillation frequency of the voltage controlled oscillator 4 has abnormally increased.
The rising edge of the reference input signal a is at the high level portion of the output C of the decoder 7. In this case, the output of the sample and hold circuit 8 will output a high level or alarm, and the frequency drift detection circuit will indicate that the phase periodic oscillator has generated a frequency drift.

FIG. 3(B) shows waveforms of various parts at the time of detecting a frequency drift in which the oscillation frequency of the voltage controlled oscillator 4 abnormally drops. In this case as well, as in the case where the oscillation frequency of the voltage controlled oscillator 4 abnormally increased, the rising edge of the reference input signal a is at the high level portion of the output C of the decoder 7, The output outputs a high level or alarm, and the frequency drift detection circuit indicates that the phase locked oscillator has generated a frequency drift.

〔Effect of the invention〕

As explained above, the present invention has a detection circuit configured with a decoder that decodes the internal state of the output side frequency divider included in the phase synchronized oscillator and a sample and hold circuit.
Since it does not involve analog processing, it has the advantage of realizing an accurate frequency drift detection circuit that operates without opening adjustment.

In addition, while conventional detection circuits required detection circuits for the high frequency side and low frequency side of the voltage controlled oscillator, the present invention can be configured with a single detection circuit, making it easy and inexpensive to manufacture. effective.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the frequency drift detection circuit of the present invention, Fig. 2 is an operating waveform diagram of the circuit shown in Fig. 1 during normal operation, and Fig. 3 is a diagram of the circuit shown in Fig. 1 during frequency drift detection. Fig. 4 is a block diagram of a conventional frequency drift detection circuit, Fig. 5 is an operating waveform diagram of the circuit shown in Fig. 4 during normal operation, and Fig. 6 is a diagram of the circuit shown in Fig. 4 during frequency drift detection. FIG. 1.10...Reference signal input terminal 2.11...
...Phase comparator 3.12...Low pass filter 4.13...
... Voltage controlled oscillator 5.14 ... Frequency divider 6.15 ... Output terminal 7 of phase synchronized oscillator ... Decoder 8.17.19. ...Sample hold circuit 20...
...OR gate 16.18...Time signal generation circuit 9.21...
...Output terminal of frequency drift detection circuit

Claims (1)

[Claims] (1) A phase-locked oscillator consisting of a decoder that decodes the internal state of an output-side frequency divider included in the phase-locked oscillator, and a sample-and-hold circuit that samples this decoder output with a reference input signal to the phase-locked oscillator. Frequency drift detection circuit.