JPS60160220A - Drift detecting circuit - Google Patents

Abstract

PURPOSE:To improve the accuracy and to attain unequivocal adjustment after the frequency is decided by using a TTL level in place of the method comparing an analog threshold value and a DC voltage to detect digitally a drift. CONSTITUTION:An input frequency enters a monostable multivibrator 9 from a terminal a and the monostable multivibrator 9 generates a pulse functioning as a threshold value detecting the drift at the leading edge of the input frequency. Moreover, an output frequency of a frequency divider 6 enters a monostable multivibtrator 8, which generates a pulse functioning as a threshold value to detect the drift at the leading edge. When the input frequency and the output frequency of the frequency divider 6 is in phase and there is no phase difference, the level of a terminal Q of a D flip-flop 10 remains ''0''. When the oscillating frequency of a voltage controlled oscillator 4 is shifted and there is a phase difference between the input frequency and the output frequency of the frequency divider 6, the level of the terminal q of the D flip-flop 10 or 11 goes to ''1'', an AND circuit 14 is turned on via an OR circuit 12 and a drift warning is transmitted from a terminal C.

Description

Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to a drift detection circuit for a phase-locked loop (PLL) circuit, and in particular, when a PLL circuit drifts from a synchronized frequency, it is possible to accurately detect the drift. This invention relates to a drift detection circuit that detects well.

(b) Prior art and problems The PLL circuit compares the phase difference between the input frequency and the output frequency so that the output frequency is synchronized with the input frequency, and when there is a difference in phase, the magnitude of the cough difference A corresponding control voltage is generated and controlled in synchronization with the voltage controlled oscillator. The control voltage is monitored, and if the control voltage increases beyond a certain range, a warning is issued as the frequency drift of the PLL circuit exceeds a specified value.

FIG. 1 is a block diagram showing an example of a PLL circuit. The output frequency of the frequency divider 6 that divides the frequency input from the terminal A and the output frequency of the voltage controlled oscillator 4 by 1/N is the output frequency of the phase comparator 1.
The phase difference is sent to the level converter 2, and the voltage based on the phase difference is sent to the filter 3. The output of the filter 3 becomes a control voltage proportional to the phase difference, and controls the oscillation frequency of the voltage controlled oscillator 4. Comparator 5 compares this control voltage with a specified value, and if the drift is large, it outputs terminal C.
Output from Further, the output frequency of the voltage controlled oscillator 4 is sent from the terminal B and is also sent to the frequency divider 6. Since the output frequency of the voltage controlled oscillator 4 deviates from the input frequency with time after synchronization and drifts, a control DC voltage is generated in the filter 3. Therefore, this DC voltage is converted to comparator 5.
Detects drift by comparing with dark value. However, the comparator 5 compares the DC voltages in an analog manner, and the control DC voltage has noise, and therefore has insufficient accuracy. Another drawback is that the comparator 5 needs to be adjusted depending on the output range of the level converter 2 and the characteristics of the voltage controlled oscillator 4.

(C) Object of the Invention The object of the present invention is to eliminate the above-mentioned drawbacks by improving accuracy by digitally detecting drift by using TTL level instead of the analog method of comparing the threshold value and DC voltage; Another object of the present invention is to provide a drift detection circuit that can be adjusted once the frequency is determined.

(d) Configuration of the Invention The configuration of the present invention is a drift detection circuit for a phase-locked loop circuit, in which a first monomultiplier operates at the leading edge of the input frequency and the output frequency of the voltage controlled oscillator is 1/1/2.
A second circuit operating at the leading edge of the output frequency of the frequency divider that divides into
a D flip-flop which inputs the output of the first mono multi to a data terminal and the output frequency of the frequency divider to a clock terminal; A D flip-flop is provided for inputting an input frequency to a clock terminal.

(e) Embodiment of the invention FIG. 2 is a block diagram of a circuit showing an embodiment of the invention.
Parts with the same functions as those in FIG. 1 are represented by the same symbols. FIG. 3 is a diagram illustrating the operation of FIG. 2.

The operations of the phase comparator 1, level converter 2, filter 3, voltage controlled oscillator 4, and frequency divider 6 are the same as those shown in FIG. 1, and their explanations will be omitted. As shown in FIG. 3 (al), the input frequency enters the monomulti 9 from terminal A, and at the rise of the input frequency, the monomulti 9 generates a pulse that becomes a dark value for detecting the amount of drift as shown in Ic. Also, as shown in (bl), the output frequency of the frequency divider 6 is input to the mono multi 8, and the output frequency of the frequency divider 6 is input to the mono multi 8
At its rise, generates a pulse that becomes the dark value for detecting the amount of drift as shown in (dl).Therefore, the monomulti 8
and 9 generate one pulse for each cycle of the respective input frequencies. In the D flip-flop 10, the pulse fdl of the monomulti 8 is input to the D terminal, and the input frequency 181 is input to the T terminal. Therefore, the input frequency (al) and the output frequency of the frequency divider 6 (
If b) is in phase and there is no phase difference, D flip-flop 10
The Q terminal of remains at "0". D flip-flop 1
1, the pulse fcl of the monomulti 9 enters the D terminal, and the T
The output frequency (b) of the frequency divider 6 is input to the terminal. Therefore, if the input frequency +8+ and the output frequency (bl) of the frequency divider 6 are in phase and there is no phase difference, the Q terminal of the D flip-flop 11 is O''
It remains as it is. Here, the oscillation frequency of the voltage controlled oscillator 4 deviates from the input frequency (al) and the output frequency (bl) of the frequency divider 6.
When a phase difference of (al
Either of the pulses indicated by and (dl, or (bl and (C1) approaches each other. Then, the D flip-flop 10 or 11
When either of the D terminals is 1", the T terminal becomes 1", and the Q terminal becomes "1". That is, when the pulses of (b) and +01 are close to each other and the D terminal of the D flip-flop is "1", the T terminal becomes 1", the Q terminal of the D flip-flop 11 becomes (
The pulses a) and Td) are close to each other and the D flip-flop 10
When the D terminal of the D flip-flop IO becomes 1'' and the T terminal becomes 1'', the Q terminal of the D flip-flop IO becomes 1''. When the Q terminal of the D flip-flop 10 or 11 becomes 1'', the AND circuit 14 is turned on via the OR circuit 12 and a drift alarm is sent from the terminal C. In order to operate as described above, the pulse width of the monomultis 8 and 9 is changed. This allows the dark value to be arbitrarily varied even if the input frequency or the voltage controlled oscillator 4 changes.

If the input frequency is cut off, it does not mean that the drift of the PLL circuit exceeds the specified value, so it is necessary to stop sending out the drift alarm. For this reason, a disconnection detection circuit 7 is provided to prevent the drift alarm from being sent out. That is, the disconnection detection circuit 7 detects the disconnection of the input frequency, and the D flip-flop 10
and reset 11.

Furthermore, during the pull-in time of the PLL circuit, since the input frequency lal and the output frequency (b) of the frequency divider 6 are out of phase, it is necessary to stop sending out the drift alarm. For this reason, a timer circuit 3 is provided to prevent the transmission of a trigger warning. That is, the timer circuit 13 initially sends out a signal to disable the AND circuit 14 until the voltage controlled oscillator 4 synchronizes and enters a stable state.

(f) Detailed Description of the Invention As described above, since the present invention digitally detects the drift of the PLL circuit, it is possible to improve the accuracy, and once the frequency is determined, the adjustment can be uniquely completed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a PLL circuit, FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention, and FIG. 3 is a diagram explaining the operation of FIG. 2. 1 is a phase comparator, 2 is a level converter, 3 is a filter, 4
1 is a voltage controlled oscillator, 5 is a comparator, 6 is a frequency divider, 7 is a disconnection detection circuit, 8.9 is a monomulti, 10.11 is a D flip-flop, and 13 is a timer circuit.

Claims (1)

[Claims] A drift detection circuit of a phase-locked loop circuit, the first monomultiplier operating at the leading edge of the input frequency and the output frequency of the frequency divider dividing the output frequency of the voltage controlled oscillator by 1/N. a second monomultiplier operating at the leading edge; a D flip-flop 7 inputting the output of the first monomultiplier to a data terminal and the output frequency of the frequency divider to a clock terminal; and the second monomultiplier. What is claimed is: 1. A drift detection circuit comprising: a D-flip float for inputting the output of the above to a data terminal and inputting the input frequency to a clock terminal.