JPH0693629B2 - Phase locked loop circuit with drift detection function - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit used in a frequency synthesizer or the like, and more particularly to a phase locked loop circuit having a drift detection function for detecting an output drift.

[Conventional technology]

The conventional drift detection circuit is configured by combining a timing circuit, a flip-flop, etc., as described in, for example, JP-A-60-160220. This conventional drift detection circuit will be described with reference to FIGS. 3 and 4.

FIG. 3 is a configuration diagram of a conventional phase locked loop circuit and drift detection circuit. The phase synchronization circuit 1 includes a phase comparator 2 for comparing the phases of an input clock IN and an output clock CLK of a frequency divider 5, a low pass filter (LPF) 3, a voltage controlled oscillator (VCO) 4, and a frequency divider. 5 and the drift detection circuit 6
Includes a monostable multivibrator 7 to make pulses of t _W width than the rising edge of the output clock CLK of the frequency divider 5, a monostable multivibrator 8 to make pulses of t _W width than the rising edge of the input clock IN, monostable multivibrator Flip-flop 9 having the output of 7 as the D input and the input clock IN as the clock input, flip-flop 10 having the output of mono-multivibrator 8 as the D input and the output clock CLK of frequency divider 5 as the clock input, and both flip-flops It comprises an OR gate 11 which takes the logical sum of the Q outputs of the amplifiers 9 and 10.

FIG. 4 is a timing chart explaining the operation of the drift detection circuit shown in FIG.

The output of the flip-flop 9 is the mono multivibrator 7
The output "1" of the above is a value punched out by the input clock IN, and the output of the flip-flop 10 is the value "1" of the mono-multivibrator 8 punched out by the phase comparison clock CLK. The drift warning signal ALM, which is the output of the OR gate 11, becomes "1" at the time of drift detection, as described below. In the state where the input and output frequencies of the phase locked loop circuit 1 match and the phases are synchronized, the rising edges of the clock inputs of both flip-flops 9 and 10 are the outputs of the mono multivibrator 7 and 8 respectively, as shown in section A of FIG. Since the "0" part has been punched out, the drift alarm signal ALM becomes "0". However, when the drift occurs, the phases of the input clock IN and the phase comparison clock CLK change and the section B in FIG.
As shown in, the rising edge of the clock input of the flip-flop 10 punches out the output "1" of the mono-multivibrator 8, so that the drift alarm signal ALM becomes "1".

[Problems to be solved by the invention]

In the above-mentioned conventional technology, since the drift detection capability depends on the output pulse width t _W determined by the constants of the mono-multivibrators 7 and 8, the mono-multivibrator (timing circuit)
There is a problem that it is easily affected by variations in the characteristics of the circuit elements constituting the device and changes over time. There is also a problem that the number of components of the circuit increases.

An object of the present invention is to provide a highly accurate and highly stable phase locked loop with drift detection, which has a small number of constituent parts.

[Means for solving problems]

The purpose of the above is to store a window waveform for drift detection in the memory for phase comparison frequency generation, which is a component of the frequency synthesizer, and compare the window waveform with the phase of the input to determine match / mismatch. Is achieved.

[Action]

When a drift occurs between the input and the output, the window waveform and the phase of the input also change. Therefore, the presence or absence of drift can be detected by punching out this window waveform with the input signal.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 is a configuration diagram of a frequency sensitizer including a drift detection circuit according to an embodiment of the present invention. IN is an input clock, OUT is an output clock, 21 is a phase comparator that detects the phase difference between the input clock IN and the output clock OUT, 22 is a low pass filter (LPF), and 23 is the input detected by the phase comparator 21. Voltage controlled oscillator (VCO) 2 that changes the oscillation frequency by the voltage according to the phase difference between clock IN and output clock OUT
Reference numeral 4 is a frequency divider for counting the output clock OUT, and 25 is a read only memory (ROM) for outputting the phase comparison clock CLK to the phase comparator 21 by the output of the frequency divider 22. Window waveform data for drift detection is also stored. A flip-flop 26 receives the window waveform from the ROM 25 at the D input and uses the input clock IN as the clock input, and outputs the drift alarm signal ALM, which has the window waveform punched out at the input clock IN, from the Q terminal.

The frequency synthesizer configured as described above is a voltage controlled oscillator.
RO from the output of 23 by the address information created by the divider 24
Phase comparison clock that controls M25 and is output from ROM25
The phase difference between the CLK and the input clock IN is detected by the phase comparator 21, and the output signal of the phase comparator 21 passing through the LPF 22 is used as the control voltage of the voltage controlled oscillator 23 to obtain the output clock OUT.

The window waveform stored in ROM25 is
As shown in FIG. 2, the waveform becomes “1” within a constant time t _W before and after the rise of the phase comparison clock CLK. In the state where the input and output frequencies match and are in phase synchronization, the input clock IN and the window waveform do not overlap, as shown in section A of FIG. 2, so the Q output of the drift detection flip-flop 26 ( ALM) is “0”. But,
When the drift occurs, the phases of the input clock IN and the window change, and the rising edge of the input clock IN and the window overlap, as shown in section B of FIG. When the rising edge of the input clock IN and the window overlap, the Q output (ALM) of the flip-flop 26 is "1".
And the drift is detected. The drift detection range is
Since the time width 2t _W of the window waveform stored in the ROM 25 is determined and the address is controlled by the output clock OUT of the ROM 25, the detection range does not change over time, and the drift can be detected stably and highly accurately.

According to the present embodiment, since only one flip-flop 26 needs to be added to the configuration of the conventional frequency synthesizer in terms of hardware, there is an effect that a frequency synthesizer equipped with a drift detection circuit can be provided at low cost.

〔The invention's effect〕

According to the present invention, it is possible to reduce the number of parts, and moreover, it is possible to detect a drift with high accuracy and high stability regardless of variations in characteristics of circuit constituent elements and aging.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a frequency synthesizer including a drift detection circuit according to an embodiment of the present invention, and FIG. 2 is a timing chart for explaining the operation of the frequency synthesizer shown in FIG. FIG. 3 is a block diagram of a phase locked loop circuit having a conventional drift detection circuit, and FIG. 4 is a timing chart for explaining the circuit operation of FIG. 22 …… Phase comparator, 22 …… LPF 23 …… Voltage controlled oscillator 24 …… Divider, 25 …… ROM 26 …… Flip-flop

Claims (1)

[Claims] 1. An oscillating means capable of controlling an oscillating frequency, a means for creating address information from an output frequency of the oscillating means, a storage means for controlling the address information creating means to output a phase comparison frequency signal, and In a phase synchronization circuit that comprises a phase comparison means for detecting a phase difference between a phase comparison frequency signal and a reference clock input from the outside, and controls the frequency of the oscillation means by the output of the phase comparison means,
The storage means is provided with information for outputting a signal indicating a permissible range or a non-permissible range of phase error, and means for detecting that the input reference clock does not overlap with the permissible range signal or overlaps with the non-permissible range signal A phase synchronization circuit with a drift detection function, which is provided.