JP2692394B2 - Phase frequency comparator - Google Patents
Phase frequency comparatorInfo
- Publication number
- JP2692394B2 JP2692394B2 JP3028061A JP2806191A JP2692394B2 JP 2692394 B2 JP2692394 B2 JP 2692394B2 JP 3028061 A JP3028061 A JP 3028061A JP 2806191 A JP2806191 A JP 2806191A JP 2692394 B2 JP2692394 B2 JP 2692394B2
- Authority
- JP
- Japan
- Prior art keywords
- input
- nand gate
- output
- terminal
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Measuring Phase Differences (AREA)
- Manipulation Of Pulses (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、位相周波数比較器に係
り、特に、無線通信装置で用いられるＰＬＬシンセサイ
ザにおける位相周波数比較器に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase frequency comparator, and more particularly to a phase frequency comparator in a PLL synthesizer used in a wireless communication device.
【０００２】[0002]
【従来の技術】近年、無線通信装置では、局部発振源と
してＰＬＬシンセサイザが多く用いられているが、位相
周波数比較器はこのＰＬＬシンセサイザの重要な構成要
素の１つである。この位相周波数比較器は、従来、例え
ば図３に示すように構成される。2. Description of the Related Art In recent years, a PLL synthesizer has been widely used as a local oscillation source in a wireless communication device, and a phase frequency comparator is one of the important constituent elements of this PLL synthesizer. This phase frequency comparator is conventionally configured, for example, as shown in FIG.
【０００３】図３において、（第１の）２入力ＮＡＮＤ
ゲ−ト１は、その第１の入力端が比較する２入力信号の
一方の信号の入力端子Ｒとなっている。この２入力ＮＡ
ＮＤゲ−ト１の出力端は、（第２の）２入力ＮＡＮＤゲ
−ト２の第１の入力端と（第１）の３入力ＮＡＮＤゲ−
ト８の第１の入力端と４入力ＮＡＮＤゲ−ト７の第１の
入力端とに接続される。２入力ＮＡＮＤゲ−トの出力端
は、（第３の）２入力ＮＡＮＤゲ−ト３の第１の入力端
と３入力ＮＡＮＤゲ−ト８の第２の入力端と４入力ＮＡ
ＮＤゲ−ト７の第２の入力端とに接続される。２入力Ｎ
ＡＮＤゲ−ト３の出力端は、２入力ＮＡＮＤゲ−ト２の
第２の入力端に接続される。In FIG. 3, a (first) two-input NAND is shown.
The gate 1 serves as an input terminal R for one of the two input signals to be compared at its first input end. This 2 input NA
The output terminal of the ND gate 1 is connected to the first input terminal of the (second) 2-input NAND gate 2 and the (first) 3-input NAND gate.
Connected to the first input terminal of the gate 8 and the first input terminal of the 4-input NAND gate 7. The output terminals of the 2-input NAND gate are the first input terminal of the (third) 2-input NAND gate 3, the second input terminal of the 3-input NAND gate 8 and the 4-input NA.
It is connected to the second input terminal of the ND gate 7. 2 inputs N
The output terminal of the AND gate 3 is connected to the second input terminal of the 2-input NAND gate 2.
【０００４】また、（第４の）２入力ＮＡＮＤゲ−ト４
は、その第１の入力端が比較する２入力信号の他方の信
号の入力端子Ｖとなっている。この２入力ＮＡＮＤゲ−
ト４の出力端は、（第５の）２入力ＮＡＮＤゲ−ト５の
第１の入力端と（第２の）３入力ＮＡＮＤゲ−ト９の第
１の入力端と４入力ＮＡＮＤゲ−ト７の第３の入力端と
に接続される。２入力ＮＡＮＤゲ−ト５の出力端は、
（第６の）２入力ＮＡＮＤゲ−ト６の第１の入力端と３
入力ＮＡＮＤゲ−ト９の第２の入力端と４入力ＮＡＮＤ
ゲ−ト７の第４の入力端とに接続される。２入力ＮＡＮ
Ｄゲ−ト６の出力端は、２入力ＮＡＮＤゲ−ト５の第２
の入力端に接続される。Also, a (fourth) 2-input NAND gate 4
Has its first input terminal serving as the input terminal V for the other of the two input signals to be compared. This 2-input NAND game
The output terminal of the gate 4 is the first input terminal of the (fifth) 2-input NAND gate 5 and the first input terminal of the (second) 3-input NAND gate 9 and the 4-input NAND gate. Connected to the third input end of the gate 7. The output terminal of the 2-input NAND gate 5 is
The (sixth) 2-input NAND gate 6 has a first input terminal 3 and
Second input terminal of input NAND gate 9 and 4-input NAND
It is connected to the fourth input terminal of the gate 7. 2-input NAN
The output end of the D gate 6 is the second input of the 2-input NAND gate 5.
Is connected to the input terminal of
【０００５】そして、４入力ＮＡＮＤゲ−ト７の出力端
は、２入力ＮＡＮＤゲ−ト３と同４の第２の入力端にそ
れぞれ接続されるとともに、３入力ＮＡＮＤゲ−ト８と
同９の第３の入力端にそれぞれ接続される。また、３入
力ＮＡＮＤゲ−ト８の出力端は、２入力ＮＡＮＤゲ−ト
１の第２の入力端と（第１の）出力バッファゲ−ト１０
の入力端とに接続され、３入力ＮＡＮＤゲ−ト９の出力
端は、２入力ＮＡＮＤゲ−ト４の第２の入力端と（第２
の）出力バッファゲ−ト１１の入力端とに接続される。
出力バッファゲ−ト１０の出力端は、比較結果の一方の
出力端子Ｕとなり、出力バッファゲ−ト１１の出力端
は、比較結果の他方の出力端子Ｄとなっている。なお、
出力バッファゲ−ト（１０、１１）は、負荷駆動能力を
高めるために常設される。The output terminal of the 4-input NAND gate 7 is connected to the second input terminals of the 2-input NAND gates 3 and 4, and the 3-input NAND gates 8 and 9 are connected. Are respectively connected to the third input ends of the. The output terminal of the 3-input NAND gate 8 is connected to the second input terminal of the 2-input NAND gate 1 and the (first) output buffer gate 10.
Of the 3-input NAND gate 9 is connected to the second input terminal of the 2-input NAND gate 4 (second terminal).
Connected to the input terminal of the output buffer gate 11.
The output end of the output buffer gate 10 is one output terminal U of the comparison result, and the output end of the output buffer gate 11 is the other output terminal D of the comparison result. In addition,
The output buffer gates (10, 11) are permanently installed to enhance the load driving capability.
【０００６】この位相周波数比較器は、入力端子（Ｒ、
Ｖ）に印加された２入力信号の位相差を検出し、その結
果を出力端子（Ｕ、Ｄ）へ送出する。その際に、位相差
は対応する出力端子へ送出するパルス列信号のパルス幅
で表し、位相の進遅は他方の出力端子を一定レベルにす
ることで表すようにしている。具体的には、図４に示す
ようになっている。図４は代表的な３種の動作例を示
す。This phase frequency comparator has input terminals (R,
The phase difference between the two input signals applied to V) is detected and the result is sent to the output terminals (U, D). At this time, the phase difference is represented by the pulse width of the pulse train signal sent to the corresponding output terminal, and the phase advance or retard is represented by setting the other output terminal at a constant level. Specifically, it is as shown in FIG. FIG. 4 shows three typical operation examples.
【０００７】図４において、同図（ａ）は入力端子Ｒと
同Ｖの入力信号は同じ周波数であるが、入力端子Ｒの入
力信号の位相が進んでいる場合を示す。この場合には、
入力端子Ｖの入力信号が高（Ｈ）レベルから低（Ｌ）レ
ベルへ変化した時点から入力端子Ｒの入力信号がＨレベ
ルからＬレベルへ変化した時点までの位相差を検出し
て、出力端子Ｕへその位相差を示すパルス幅を有するパ
ルス列信号を送出する。出力端子ＤへはＨレベルのレベ
ル信号が送出される。In FIG. 4, (a) of FIG. 4 shows the case where the input signals of the input terminal R and the input V have the same frequency, but the phase of the input signal of the input terminal R is advanced. In this case,
The phase difference from the time when the input signal of the input terminal V changes from the high (H) level to the low (L) level to the time when the input signal of the input terminal R changes from the H level to the L level is detected, and the output terminal A pulse train signal having a pulse width indicating the phase difference is transmitted to U. A level signal of H level is sent to the output terminal D.
【０００８】同図（ｂ）は入力端子Ｒと同Ｖの入力信号
は同じ周波数であるが、入力端子Ｖの入力信号の位相が
進んでいる場合を示す。この場合には、入力端子Ｒの入
力信号がＨレベルからＬレベルへ変化した時点から入力
端子Ｖの入力信号がＨレベルからＬレベルへ変化した時
点までの位相差を検出して、出力端子Ｄへその位相差を
示すパルス幅を有するパルス列信号を送出する。出力端
子ＵへはＨレベルのレベル信号が送出される。FIG. 2B shows a case where the input signals of the input terminals R and V have the same frequency, but the phase of the input signal of the input terminal V is advanced. In this case, the phase difference from the time when the input signal of the input terminal R changes from the H level to the L level to the time when the input signal of the input terminal V changes from the H level to the L level is detected, and the output terminal D A pulse train signal having a pulse width indicating the phase difference of the navel is transmitted. An H level signal is sent to the output terminal U.
【０００９】同図（ｃ）は入力端子Ｒと同Ｖの入力信号
は異なる周波数であり、入力端子Ｒの入力信号の周波数
が入力端子Ｖの入力信号の周波数の１．５倍である場合
を示す。この場合には、入力端子Ｖの入力信号がＨレベ
ルからＬレベルへ変化した時点から入力端子Ｒの入力信
号がＨレベルからＬレベルへ変化した時点までの位相差
を検出して、出力端子Ｕへその位相差を示すパルス幅を
有するパルス列信号を送出する。出力端子ＤへはＨレベ
ルのレベル信号が送出される。なお、出力端子Ｕへの出
力信号は、入力端子Ｒの入力信号の３周期、又は、入力
端子Ｖの入力信号の２周期を１周期とした同じパタ−ン
を繰り返す信号となっている。In FIG. 1C, the input signals of the input terminals R and V have different frequencies, and the frequency of the input signal of the input terminal R is 1.5 times the frequency of the input signal of the input terminal V. Show. In this case, the phase difference from the time when the input signal of the input terminal V changes from the H level to the L level to the time when the input signal of the input terminal R changes from the H level to the L level is detected, and the output terminal U A pulse train signal having a pulse width indicating the phase difference of the navel is transmitted. A level signal of H level is sent to the output terminal D. The output signal to the output terminal U is a signal that repeats the same pattern with one cycle consisting of three cycles of the input signal of the input terminal R or two cycles of the input signal of the input terminal V.
【００１０】[0010]
【発明が解決しようとする課題】上述した従来の位相周
波数比較器では、図５に示すように、２つの入力信号の
位相が接近した零付近に、出力パルスを正常に発生でき
ない範囲（いわゆる不感帯）が存在するという問題があ
る。具体的に言えば、図５は、横軸が２入力端子に印加
された２入力信号の位相差で、縦軸が２出力端子へ送出
される２出力信号を積分して得た直流成分の差を表して
いる。これは、入力位相差に対する出力電圧の感度を示
しているのであり、直線の傾きが復調感度である。図５
は、復調感度が入力位相差零付近で急激に変化すること
を示している。従って、このような位相周波数比較器を
備えるＰＬＬシンセサイザでは、位相差零付近での動作
が不安定化するのである。In the conventional phase frequency comparator described above, as shown in FIG. 5, in the vicinity of zero where the phases of two input signals are close to each other, a range in which an output pulse cannot be normally generated (a so-called dead zone). ) Exists. Specifically, in FIG. 5, the horizontal axis represents the phase difference between the two input signals applied to the two input terminals, and the vertical axis represents the DC component obtained by integrating the two output signals sent to the two output terminals. Represents the difference. This shows the sensitivity of the output voltage to the input phase difference, and the slope of the straight line is the demodulation sensitivity. FIG.
Indicates that the demodulation sensitivity changes abruptly near the input phase difference of zero. Therefore, in the PLL synthesizer including such a phase frequency comparator, the operation becomes unstable near the phase difference of zero.
【００１１】前記不感帯を生ずる原因は、出力バッファ
ゲ−トにある。即ち、出力バッファゲ−トには、動作遅
延時間や波形のなまり等があるので、出力し得るパルス
の最小時間幅が存在する。従って、位相差零付近では、
３入力ＮＡＮＤゲ−トの出力パルス幅は非常に狭く出力
バッファゲ−トの出力し得るパルスの最小時間幅以下と
なるので、出力バッファゲ−トは位相差零付近での位相
差情報を出力できず、不感帯が生ずるのである。しか
し、出力バッファゲ−トは、負荷駆動能力を高めるため
に不可欠であるので、これを存置したままでの改善が望
まれている。The cause of the dead zone is the output buffer gate. That is, since the output buffer gate has an operation delay time and a waveform rounding, there is a minimum time width of a pulse that can be output. Therefore, near zero phase difference,
Since the output pulse width of the 3-input NAND gate is very narrow and is less than the minimum time width of the pulse that the output buffer gate can output, the output buffer gate cannot output the phase difference information near the phase difference zero. , A dead zone occurs. However, since the output buffer gate is indispensable for enhancing the load driving capability, it is desired to improve it while keeping it.
【００１２】本発明の目的は、出力バッファゲ−トを存
置した状態で、不感帯を生じない位相周波数比較器を提
供することにある。It is an object of the present invention to provide a phase frequency comparator which does not produce a dead zone in the state where the output buffer gate is kept.
【００１３】[0013]
【課題を解決するための手段】前記目的を達成するため
に、本発明の位相周波数比較器は次の如き構成を有す
る。即ち、本発明の位相周波数比較器は、比較する２入
力信号の一方が第１の入力端に印加される第１の２入力
ＮＡＮＤゲ−トの出力端が第２の２入力ＮＡＮＤゲ−ト
の第１の入力端と第１の３入力ＮＡＮＤゲ−トの第１の
入力端と４入力ＮＡＮＤゲ−トの第１の入力端とに接続
され； 前記第２の２入力ＮＡＮＤゲ−トの出力端が第
３の２入力ＮＡＮＤゲ−トの第１の入力と前記第１の３
入力ＮＡＮＤゲ−トの第２の入力端と前記４入力ＮＡＮ
Ｄゲ−トの第２の入力端とに接続され； 前記第３の２
入力ＮＡＮＤゲ−トの出力端が前記第２の２入力ＮＡＮ
Ｄゲ−トの第２の入力端に接続され； 比較する２入力
信号の他方が第１の入力端に印加される第４の２入力Ｎ
ＡＮＤゲ−トの出力端が第５の２入力ＮＡＮＤゲ−トの
第１の入力端と第２の３入力ＮＡＮＤゲ−トの第１の入
力端と前記４入力ＮＡＮＤゲ−トの第３の入力端とに接
続され； 前記第５の２入力ＮＡＮＤゲ−トの出力端が
第６の２入力ＮＡＮＤゲ−トの第１の入力と前記第２の
３入力ＮＡＮＤゲ−トの第２の入力端と前記４入力ＮＡ
ＮＤゲ−トの第４の入力端とに接続され；前記第６の２
入力ＮＡＮＤゲ−トの出力端が前記第５の２入力ＮＡＮ
Ｄゲ−トの第２の入力端に接続され； 前記４入力ＮＡ
ＮＤゲ−トの出力端が前記第３及び第６の２入力ＮＡＮ
Ｄゲ−トの第２の入力端にそれぞれ接続され； 前記第
１の３入力ＮＡＮＤゲ−トの出力端が前記第１の２入力
ＮＡＮＤゲ−トの第２の入力端と第１の出力バッファゲ
−トの入力端とに接続され； 前記第２の３入力ＮＡＮ
Ｄゲ−トの出力端が前記第４の２入力ＮＡＮＤゲ−トの
第２の入力端と第２の出力バッファゲ−トの入力端とに
接続され； 第１及び第２の出力バッファゲ−トの出力
端から比較結果をそれぞれ出力するようにした位相周波
数比較器において； 共通接続される前記第１及び第２
の３入力ＮＡＮＤゲ−トの第３の入力端と前記４入力Ｎ
ＡＮＤゲ−トの出力端との間を遅延素子を介して接続し
たこと； を特徴とするものである。In order to achieve the above object, the phase frequency comparator of the present invention has the following configuration. That is, in the phase frequency comparator of the present invention, the output terminal of the first 2-input NAND gate to which one of the two input signals to be compared is applied to the first input terminal is the second 2-input NAND gate. Is connected to the first input terminal of the first 3-input NAND gate and the first input terminal of the 4-input NAND gate; and the second 2-input NAND gate. Is connected to the first input of the third 2-input NAND gate and the first 3
The second input terminal of the input NAND gate and the 4-input NAN
Connected to the second input of the D-gate;
The output terminal of the input NAND gate is the second 2-input NAN.
A fourth input N connected to the second input of the D gate; the other of the two input signals to be compared is applied to the first input
The output terminal of the AND gate is the first input terminal of the fifth 2-input NAND gate, the first input terminal of the second 3-input NAND gate, and the third input terminal of the 4-input NAND gate. The output terminal of the fifth 2-input NAND gate is connected to the first input of the sixth 2-input NAND gate and the second terminal of the second 3-input NAND gate. Input end and the 4 input NA
Connected to the fourth input of the ND gate; the sixth 2
The output terminal of the input NAND gate is the fifth 2-input NAN.
Connected to the second input of the D-gate; the 4-input NA
The output terminal of the ND gate has the third and sixth 2-input NANs.
The output terminal of the first 3-input NAND gate is connected to the second input terminal of the D-gate, and the output terminal of the first 3-input NAND gate is connected to the second input terminal and the first output of the first 2-input NAND gate. Connected to the input of a buffer gate; the second three-input NAN
The output terminal of the D gate is connected to the second input terminal of the fourth 2-input NAND gate and the input terminal of the second output buffer gate; first and second output buffer gates. Phase frequency comparators configured to output comparison results from respective output terminals of the first and second common-connected
3 input NAND gate of the third input terminal and the 4 input N
It is connected to the output end of the AND gate via a delay element.
【００１４】[0014]
【作用】次に、前記の如く構成される本発明の位相周波
数比較器の作用を説明する。本発明では、４入力ＮＡＮ
Ｄゲ−トの出力を遅延してから第１及び第２の３入力Ｎ
ＡＮＤゲ−トの第３の入力端に入力するようにしてあ
る。その結果、第１及び第４の２入力ＮＡＮＤゲ−トが
ＬレベルからＨレベルに変化してから第１及び第２の出
力バッファゲ−トがＨレベルからＬレベルに変化するま
での時間幅が広がるので、第１及び第２の３入力ＮＡＮ
Ｄゲ−トの出力パルス幅が広がる。つまり、出力バッフ
ァゲ−トは位相差零付近において十分な所定パルス幅の
信号を出力でき、不感帯をなくすことができる。Next, the operation of the phase frequency comparator of the present invention constructed as described above will be described. In the present invention, 4-input NAN
After delaying the output of the D gate, the first and second three inputs N
Input is made to the third input terminal of the AND gate. As a result, the time width from the change of the first and fourth 2-input NAND gates from the L level to the H level until the change of the first and second output buffer gates from the H level to the L level is increased. Since it spreads, the first and second three-input NAN
The output pulse width of the D gate is widened. That is, the output buffer gate can output a signal having a sufficient predetermined pulse width in the vicinity of the phase difference of zero and eliminate the dead zone.
【００１５】[0015]
【実施例】以下、本発明の実施例を図面を参照して説明
する。図１は、本発明の一実施例に係る位相周波数比較
器を示す。なお、図３と同一構成部分には同一符号を付
し、その説明を省略する。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a phase frequency comparator according to an embodiment of the present invention. The same components as those in FIG. 3 are designated by the same reference numerals and the description thereof will be omitted.
【００１６】図１において、３入力ＮＡＮＤゲ−ト８と
同９の共通接続される第３の入力端同士と４入力ＮＡＮ
Ｄゲ−ト７の出力端との間に遅延素子１２を介在させて
ある。In FIG. 1, three-input NAND gates 8 and 9 are commonly connected to each other and have a three-input NAND gate and a four-input NAN.
A delay element 12 is interposed between the output terminal of the D gate 7 and the output terminal.
【００１７】その結果、２入力ＮＡＮＤゲ−ト（１、
４）がＬレベルからＨレベルに変化してから出力バッフ
ァゲ−ト（１０、１１）がＨレベルからＬレベルに変化
するまでの時間幅が広がるので、３入力ＮＡＮＤゲ−ト
（８、９）の出力パルス幅が広がる。従って、出力バッ
ファゲ−ト（１０、１１）は位相差零付近において十分
な所定パルス幅の信号を出力でき、図２に示すように、
不感帯をなくすことができる。As a result, the 2-input NAND gate (1,
3) NAND gates (8, 9) because the time width from the change of 4) from L level to H level until the output buffer gates (10, 11) change from H level to L level is widened. The output pulse width of is expanded. Therefore, the output buffer gates (10, 11) can output a signal with a sufficient predetermined pulse width near the phase difference of zero, and as shown in FIG.
The dead zone can be eliminated.
【００１８】[0018]
【発明の効果】以上説明したように、本発明の位相周波
数比較器によれば、４入力ＮＡＮＤゲ−トの出力を遅延
してから第１及び第２の３入力ＮＡＮＤゲ−トの第３の
入力端に入力するようにしたので、出力バッファゲ−ト
は位相差零付近において十分な所定パルス幅の信号を出
力でき、不感帯をなくすことができる効果がある。As described above, according to the phase frequency comparator of the present invention, after delaying the output of the 4-input NAND gate, the third of the first and second 3-input NAND gates is delayed. The output buffer gate can output a signal having a sufficient predetermined pulse width in the vicinity of zero phase difference, so that the dead zone can be eliminated.
【図１】本発明の一実施例に係る位相周波数比較器の回
路図である。FIG. 1 is a circuit diagram of a phase frequency comparator according to an embodiment of the present invention.
【図２】本発明回路による位相差−出力電圧の関係図で
ある。FIG. 2 is a phase difference-output voltage relationship diagram according to the circuit of the present invention.
【図３】従来の位相周波数比較器の回路図である。FIG. 3 is a circuit diagram of a conventional phase frequency comparator.
【図４】位相周波数比較器の一般的な動作を示すタイム
チャ−トである。FIG. 4 is a time chart showing a general operation of a phase frequency comparator.
【図５】従来例回路による位相差−出力電圧の関係図で
ある。FIG. 5 is a relationship diagram of a phase difference and an output voltage according to a conventional example circuit.
１ ２入力ＮＡＮＤゲ−ト ２ ２入力ＮＡＮＤゲ−ト ３ ２入力ＮＡＮＤゲ−ト ４ ２入力ＮＡＮＤゲ−ト ５ ２入力ＮＡＮＤゲ−ト ６ ２入力ＮＡＮＤゲ−ト ７ ４入力ＮＡＮＤゲ−ト ８ ３入力ＮＡＮＤゲ−ト ９ ３入力ＮＡＮＤゲ−ト １０ 出力バッファゲ−ト １１ 出力バッファゲ−ト １２ 遅延素子 1 2-input NAND gate 2 2-input NAND gate 3 2-input NAND gate 4 2-input NAND gate 5 2-input NAND gate 6 2-input NAND gate 7 4-input NAND gate 8 3-input NAND gate 9 3-input NAND gate 10 Output buffer gate 11 Output buffer gate 12 Delay element
Claims (1)
端に印加される第１の２入力ＮＡＮＤゲ−トの出力端が
第２の２入力ＮＡＮＤゲ−トの第１の入力端と第１の３
入力ＮＡＮＤゲ−トの第１の入力端と４入力ＮＡＮＤゲ
−トの第１の入力端とに接続され； 前記第２の２入力
ＮＡＮＤゲ−トの出力端が第３の２入力ＮＡＮＤゲ−ト
の第１の入力と前記第１の３入力ＮＡＮＤゲ−トの第２
の入力端と前記４入力ＮＡＮＤゲ−トの第２の入力端と
に接続され； 前記第３の２入力ＮＡＮＤゲ−トの出力
端が前記第２の２入力ＮＡＮＤゲ−トの第２の入力端に
接続され； 比較する２入力信号の他方が第１の入力端
に印加される第４の２入力ＮＡＮＤゲ−トの出力端が第
５の２入力ＮＡＮＤゲ−トの第１の入力端と第２の３入
力ＮＡＮＤゲ−トの第１の入力端と前記４入力ＮＡＮＤ
ゲ−トの第３の入力端とに接続され； 前記第５の２入
力ＮＡＮＤゲ−トの出力端が第６の２入力ＮＡＮＤゲ−
トの第１の入力と前記第２の３入力ＮＡＮＤゲ−トの第
２の入力端と前記４入力ＮＡＮＤゲ−トの第４の入力端
とに接続され； 前記第６の２入力ＮＡＮＤゲ−トの出
力端が前記第５の２入力ＮＡＮＤゲ−トの第２の入力端
に接続され； 前記４入力ＮＡＮＤゲ−トの出力端が前
記第３及び第６の２入力ＮＡＮＤゲ−トの第２の入力端
にそれぞれ接続され； 前記第１の３入力ＮＡＮＤゲ−
トの出力端が前記第１の２入力ＮＡＮＤゲ−トの第２の
入力端と第１の出力バッファゲ−トの入力端とに接続さ
れ； 前記第２の３入力ＮＡＮＤゲ−トの出力端が前記
第４の２入力ＮＡＮＤゲ−トの第２の入力端と第２の出
力バッファゲ−トの入力端とに接続され； 第１及び第
２の出力バッファゲ−トの出力端から比較結果をそれぞ
れ出力するようにした位相周波数比較器において；共通
接続される前記第１及び第２の３入力ＮＡＮＤゲ−トの
第３の入力端と前記４入力ＮＡＮＤゲ−トの出力端との
間を遅延素子を介して接続したこと； を特徴とする位
相周波数比較器。1. An output terminal of a first 2-input NAND gate, to which one of two input signals to be compared is applied to a first input terminal, is a first input terminal of a second 2-input NAND gate. And the first 3
An input end of the input NAND gate and a first input end of the 4-input NAND gate are connected; and an output end of the second 2-input NAND gate is a third 2-input NAND gate. -The first input of the NAND gate and the second input of the first 3-input NAND gate
Is connected to the second input terminal of the 4-input NAND gate; and the output terminal of the third 2-input NAND gate is connected to the second input terminal of the second 2-input NAND gate. Connected to an input end; the other end of the two input signals to be compared is applied to the first input end, and the output end of the fourth two-input NAND gate is the first input of the fifth two-input NAND gate. End and a first input end of a second 3-input NAND gate and the 4-input NAND.
It is connected to the third input terminal of the gate; the output terminal of the fifth 2-input NAND gate is the sixth 2-input NAND gate.
Connected to the first input of the gate, the second input of the second 3-input NAND gate and the fourth input of the 4-input NAND gate; and the sixth 2-input NAND gate. -The output terminal of the 4-input NAND gate is connected to the second input terminal of the fifth 2-input NAND gate; and the output terminal of the 4-input NAND gate is connected to the third and sixth 2-input NAND gates. Of the first three-input NAND gate
An output end of the second 3-input NAND gate is connected to a second input end of the first 2-input NAND gate and an input end of the first output buffer gate. Is connected to the second input terminal of the fourth two-input NAND gate and the input terminal of the second output buffer gate; the comparison results are output from the output terminals of the first and second output buffer gates. In a phase frequency comparator adapted to output respectively, between the third input terminal of the first and second 3-input NAND gates and the output terminal of the 4-input NAND gate which are commonly connected. A phase frequency comparator characterized by being connected via a delay element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3028061A JP2692394B2 (en) | 1991-01-29 | 1991-01-29 | Phase frequency comparator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3028061A JP2692394B2 (en) | 1991-01-29 | 1991-01-29 | Phase frequency comparator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04253423A JPH04253423A (en) | 1992-09-09 |
| JP2692394B2 true JP2692394B2 (en) | 1997-12-17 |
Family
ID=12238248
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3028061A Expired - Lifetime JP2692394B2 (en) | 1991-01-29 | 1991-01-29 | Phase frequency comparator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2692394B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW538597B (en) * | 1998-03-31 | 2003-06-21 | Fujitsu General Co Ltd | Phase lock loop circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58194433A (en) * | 1982-05-08 | 1983-11-12 | Mitsubishi Electric Corp | Pll circuit |
-
1991
- 1991-01-29 JP JP3028061A patent/JP2692394B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04253423A (en) | 1992-09-09 |
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