JPS58194433A - Pll circuit - Google Patents

Abstract

PURPOSE:To eliminate a discontinuous region of the characteristics of a PLL circuit and to prevent the instability during the acquisition of synchronism, by setting the transmission delay time of a phase comparator at a value larger than the minimum answer pulse width time of a charge pump circuit of the following stage. CONSTITUTION:Delaying inverters 35 and 36 are provided at the output side of an NAND gate 11 of a phase comparator 1 which constitutes a PLL circuit. The delay times of the inverters 35 and 36 are set larger than the minimum answer pulse width of a charge pump circuit 2. As a result, no discontinuation is produced to the phase pair VCO controlling voltage characteristics of the PLL circuit although the frequency fX to be compared is perfectly synchronous with the reference frequency fR. This process prevents the instability of the PLL circuit during the acquisition of synchronism. In addition, a comparatively low answer speed is avaiable with the circuit 2. This process facilitates the design of the circuit 2.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of a phase comparator constituting a tiPLL circuit, particularly a KPLL circuit.

P L L (Phas@Locked Loop)
When configuring a digital comparator, a digital comparator type phase comparator is often used.

FIG. 11 is a block diagram of the phase comparator 1 and the subsequent charge pump circuit 2, and FIG. 2 is a timing chart of the phase comparator.

In Figures 1 and 2, S is the input terminal of the compared frequency fx, 4#'1 is the input terminal of the reference frequency fR, I'S6
, Te, 8, 9, 1G,
11, 12, 18 are N
AND game), 14, 16 are WAND game) 12
．． 18 output, 16.1711 i/parta, 18.19
is an NPN transistor, 2G is a power supply terminal, 21 is the output of the charge pump circuit, 24, 2&, 26
, in.

gs, so, 5oVi respectively NAND gate Is, 6°7.8, 9.10.11 output, 81
, jlg is the compared frequency fx8 and the reference same wave number fR
When 4 is synchronized and 9 is WAND game), the output pulse width is 12 and 18.

The phase difference between the 8 compared wave numbers fx input to the input terminal 8.4 and the reference frequency h is output to the NAND gate 12.11. The drawback of the conventional type is that at the time of synchronization pull-in, that is, when the phases of the compared frequency /X and the reference frequency /H become close to the synchronized state, the pulse width of the waveform 14 or 16 output to the NAND gate 11.18 becomes narrow. (In the end, when the compared same wave number and the reference frequency 711 are completely synchronized, the WAND game) 1ffi, the waveform 14 output to 11, lji's /(rus width 11.!Ig
The time width corresponds to the propagation delay time of the ND gate 11. ), the charge pump circuit 2 connected to the subsequent stage becomes unable to respond. For example, let us now consider a case in which the charge pump circuit 8 has a characteristic that it can only respond to pulses with a width of 80 nS or more, and the propagation delay time of the WAND game (11) is 10n8.

If the phases of the compared same wave number fx and the reference same wave number /H are synchronized and the phase difference becomes BOn8 or less, the output waveform 14.15 of the WAND game) lil, 1 is the pulse @
81, 8g/d, liOnB or less, charge pump times 11! #i Unable to respond. As a result, the characteristics of the phase comparator 1 and the charge pump circuit 8 have a discontinuous region 8 as shown in FIG. When a PLLI is configured with a phase comparator l and a charge pump circuit having such characteristics, in the discontinuous region 38.

The loop is disturbed and the wave number stability of question 9 deteriorates. In addition, in the case of radio, television tuners, etc., this leads to a deterioration of the 4 ratio.In order to solve the above problem, the present invention sets the propagation delay time tpi of the phase comparator constituting the PLL circuit to the minimum value of the charge pump circuit i@8. It is at the point where it is larger than the response pulse width. By doing this, even when the compared frequency lx and the reference frequency /R are completely synchronized, the charge pump circuit 2
responds, so the characteristic line has no discontinuous lji region as shown in FIG. In the diagram, the offset 34 occurs because there is a moment when the source side transistor 18 and the sink side transistor 19 of the charge pump circuit 2 are simultaneously turned on, but this is caused by the LPF (1°°1 °°°1 “tar) [″]Route 0
Examining the characteristics - t, bc and K, "(, it is possible to cancel.

A specific embodiment of the present invention is shown in the diagram below.

The difference from the conventional one is that there are 8 stages of delay inverters on the output side of the NAND game) 11! ! , 16t"j!
Even if the compared frequency −/X and the reference frequency In 2>' are completely synchronized, the delay time will be equivalent to the 8 gates of the WAND gate (WAND gate) 11 and the delay inverters 86 and 86, so the subsequent charge pump circuit sFi There is an advantage that a relatively slow response speed is sufficient, and the circuit design of the charge pump circuit 80 is facilitated.

As described above, the present invention eliminates the discontinuous region in the characteristics of the PLL circuit by making the propagation delay time of the phase comparator that constitutes the PLL circuit larger than the minimum response pulse width time of the charge pump circuit in the subsequent stage. It is possible to prevent the PLL circuit from becoming unstable at the time of synchronization pull-in.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a conventional phase comparator and charge pump circuit, and FIG. 8 is a timing chart of the phase comparator.
Figure 6 is a characteristic diagram of a conventional phase comparator and charge pump, Figure 6 is a characteristic diagram of a phase comparator and charge pump improved by the present invention, and Figure 6 is a characteristic diagram showing an embodiment of the present invention. FIG. 2 is a configuration diagram of a comparator and a charge pump circuit. In the figure, l is a phase comparator, f is a charge pump circuit, and s1
Numbers are the input terminals of the compared frequency fx and the reference frequency In, 5, 6, 7, 8, 9, 10°11,
12, 18 are WAND gates, 811t, 86
is a delay inverter. In Figure 1, the same reference numerals indicate the same or equivalent parts. Agent Makoto Kuzuno - Figure 1 No Saemo ≧ Mi Showa
Date of the year: Mr. Commissioner of the Japan Patent Office 1, Indication of the case: Mochieisho 6-711811 No. 2
, Name of the invention PLL circuit 3, Relationship with the supplementary IE case Patent applicant address Chiyo F, Tokyo ((2-2-3, Okibi-no-uchi) Name (601) Mitsubishi Electric Co., Ltd. representative old piece Yuni Hachibe 4 Agent Address: Marunouchi-cho, Chiyo ILI-ku, Tokyo [12]
Figure 1 of No. 3 No. 5, Drawing 6 subject to amendment, Contents of amendment is corrected as shown in the attached sheet. that's all:(

Claims (1)

[Claims] 111 In a PLL circuit including a phase comparator that generates an output corresponding to a phase difference between a reference frequency and a compared frequency, and a charge pump circuit that responds to the output of this phase comparator, the phase A PLL circuit characterized in that the propagation delay time of the comparator is made larger than the minimum response pulse width time of the charge pump circuit. The PLL circuit according to claim 1, wherein the phase comparator includes a delay inverter.