JPS588230U

JPS588230U - pulse delay circuit

Info

Publication number: JPS588230U
Application number: JP1981102475U
Authority: JP
Inventors: 徳山　義夫
Original assignee: 日本ビクター株式会社
Priority date: 1981-07-10
Filing date: 1981-07-10
Publication date: 1983-01-19
Also published as: JPH0119471Y2

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は本考案回路の一実施例を示す回路図、第２図Ａ
−Ｅ及び第３図Ａ−Ｄは夫々第１図の動作説明用信号波
形図である。１・・・入力端子、′２・・・単安定マルチバイブレー
タ（モノマルチ）、３・・・遅延回路、６・・・コンパ
レータ、８・・・フリップフロップ、９・・・出力端子
、Ｔｒ・・・スイッチングトランジスタ、ｖＲ・・・可
変抵抗器、Ｃ１・・・充放電用コンデンサ。Figure 1 is a circuit diagram showing an embodiment of the circuit of the present invention, Figure 2A
-E and FIGS. 3A to 3D are signal waveform diagrams for explaining the operation of FIG. 1, respectively. 1... Input terminal, '2... Monostable multivibrator (mono multi), 3... Delay circuit, 6... Comparator, 8... Flip-flop, 9... Output terminal, Tr. ...Switching transistor, vR...Variable resistor, C1...Charging/discharging capacitor.

Claims

[Scope of utility model registration request]

In a pulse delay circuit that has a variable delay amount range that is approximately equal to the period of an input pulse and outputs a pulse with a desired amount of delay at the same repetition frequency as the input pulse, a pulse delay circuit that delays the input pulse for an extremely short time. 1 delay circuit;
The output delay pulse of the first delay circuit is supplied, and the terminal voltage of the capacitor whose charge and discharge are controlled by the delay pulse is compared in level with a reference voltage, and this level comparison output is compared with the input pulse or a pulse whose phase is synchronized therewith. a second delay circuit that outputs a delayed pulse from an output terminal of a flip-flop which is brought into a first stable state by the OR output of and which is brought into a second stable state by the delayed pulse; A pulse delay circuit configured to variably control the time constant of a capacitor in the delay circuit to output a pulse with a desired amount of delay and to limit the maximum amount of delay to a value approximately equal to the period of the human pulse. .