JPS59100323U

JPS59100323U - Supply power control circuit

Info

Publication number: JPS59100323U
Application number: JP19394182U
Authority: JP
Inventors: 馬場　哲郎; 吾妻　敏幸
Original assignee: 東北金属工業株式会社
Priority date: 1982-12-23
Filing date: 1982-12-23
Publication date: 1984-07-06

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

、図は本考案の一実施例を示すもので、第１図は、ゼロ
クロス検出回路部の一例を直流定電圧電源とともに示す
回路図、第２図は、供給電力選択および電力制御部を示
す回路図、第３図は、各部のパルスのタイミングを示す
図でａは第１図の回路の出力であるゼロクロスパルス、
ｂ〜ｆは第２図中のに〜０点のパルスをそれぞれ示し、
第４図は第２図でＢ端子を選択した場合のゼロクロスス
イッチングを説明する図で、ａは交流波形、ｂはサイリ
スタＴＲのトリガ波形を宗す。１・・・分周器、２〜６・・・アンドゲート、７・・・
オアゲート、Ａ〜Ｅ・・・電力選択信号入力端子、ＴＲ
・・・サイリスタ。, the figures show one embodiment of the present invention, FIG. 1 is a circuit diagram showing an example of the zero cross detection circuit section together with a DC constant voltage power supply, and FIG. 2 is a circuit diagram showing the supply power selection and power control section. Figures 3 and 3 are diagrams showing the timing of pulses in each part, where a is the zero-cross pulse that is the output of the circuit in Figure 1,
b to f indicate the pulses at point ~0 in Figure 2, respectively;
FIG. 4 is a diagram illustrating zero-cross switching when terminal B is selected in FIG. 2, where a represents an AC waveform and b represents a trigger waveform of the thyristor TR. 1... Frequency divider, 2-6... AND gate, 7...
OR gate, A to E...power selection signal input terminal, TR
...thyristor.

Claims

[Scope of utility model registration request]

A zero-cross pulse generator that generates pulses synchronized with the seven cross points of the AC power supply for power supply; n (n is an integer) power selection signal input terminals for inputting signals for selecting supply power, respectively; ; n AND gates each having a control input terminal connected to each of the power selection signal input terminals; with the zero-crossing pulse as input, and each period of 1, 2, . . . n times the zero-crossing pulse; a frequency divider, which outputs a pulse having a value of 0 in synchronization with the zero-crossing pulse, and connects the n outputs to the other input terminals of the n AND gates; An OR gate that takes all outputs as input and generates an output pulse when any of the AND gates has an output; it is inserted and connected to the power supply line and is fired when there is an output pulse from the OR gate. 1. A power supply control circuit comprising: a power supply control circuit which is capable of controlling supply power selection by inputting a signal to any of the power selection signal input terminals.