JPS6085434U - pulse delay device - Google Patents
pulse delay deviceInfo
- Publication number
- JPS6085434U JPS6085434U JP1983176937U JP17693783U JPS6085434U JP S6085434 U JPS6085434 U JP S6085434U JP 1983176937 U JP1983176937 U JP 1983176937U JP 17693783 U JP17693783 U JP 17693783U JP S6085434 U JPS6085434 U JP S6085434U
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- circuit
- voltage
- delay device
- conversion circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Pulse Circuits (AREA)
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の実施例のブロック図、第２図ａ ％
ｈは第１図の動作波形図である。図において１．６・・
・フリップフロップ、２・・・クロックパルス発生器、
３・・・クロックゲート回路、４・・・計数回路、５・
・・遅延時間設定部、７・・・定電流源、８・・・制御
回路、９・・・コンデンサ、１０・・・電圧比較回路、
１１・・・サンプルホールド回路、１２・・・ランプ電
圧 ・発生回路である。Figure 1 is a block diagram of an embodiment of the present invention, Figure 2 a%
h is an operating waveform diagram of FIG. 1; In the figure 1.6...
・Flip-flop, 2...clock pulse generator,
3... Clock gate circuit, 4... Counting circuit, 5.
... Delay time setting section, 7... Constant current source, 8... Control circuit, 9... Capacitor, 10... Voltage comparison circuit,
11... Sample and hold circuit, 12... Lamp voltage/generation circuit.
Claims (1)
延を与えるパルス遅延装置において、前記入力パルス信
号の入力時から前記基準パルスの１個目までの時間差を
電圧に変換する電圧変換回路と、この電圧変換回路の出
力電圧を保持するサンプルホールド回路と、前記基準パ
ルスの１個目から前記設定数から１個少い数まで前記基
準パルスを計数するパルス計数回路と、このパルス計数
回路の計数完了時から前記電圧変換回路の出力電圧と逆
の傾斜をもつランプ電圧を発生するランプ電圧発生回路
と、このランプ電圧発生回路および前記電圧変換回路の
出力電圧を比較し一致した時にパルスを出力する電圧比
較回路とを有することを特徴とするパルス遅延装置。In a pulse delay device that delays an input pulse signal by a predetermined number of reference pulses, a voltage conversion circuit that converts a time difference from the input of the input pulse signal to the first reference pulse into a voltage; A sample and hold circuit that holds the output voltage of this voltage conversion circuit, a pulse counting circuit that counts the reference pulses from the first reference pulse to a number less than the set number by one, and a counting circuit of this pulse counting circuit. A lamp voltage generation circuit that generates a lamp voltage having a slope opposite to the output voltage of the voltage conversion circuit from the time of completion compares the output voltages of this lamp voltage generation circuit and the voltage conversion circuit, and outputs a pulse when they match. A pulse delay device comprising a voltage comparison circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1983176937U JPS6085434U (en) | 1983-11-16 | 1983-11-16 | pulse delay device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1983176937U JPS6085434U (en) | 1983-11-16 | 1983-11-16 | pulse delay device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6085434U true JPS6085434U (en) | 1985-06-12 |
Family
ID=30384537
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1983176937U Pending JPS6085434U (en) | 1983-11-16 | 1983-11-16 | pulse delay device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6085434U (en) |
-
1983
- 1983-11-16 JP JP1983176937U patent/JPS6085434U/en active Pending
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