JPH0284335U - - Google Patents

Info

Publication number
JPH0284335U
JPH0284335U JP1988165403U JP16540388U JPH0284335U JP H0284335 U JPH0284335 U JP H0284335U JP 1988165403 U JP1988165403 U JP 1988165403U JP 16540388 U JP16540388 U JP 16540388U JP H0284335 U JPH0284335 U JP H0284335U
Authority
JP
Japan
Prior art keywords
surface mount
package
accommodating
mount package
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1988165403U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988165403U priority Critical patent/JPH0284335U/ja
Publication of JPH0284335U publication Critical patent/JPH0284335U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/1627—Disposition stacked type assemblies, e.g. stacked multi-cavities

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

【図面の簡単な説明】
第１図は、本考案の一実施例の表面実装型パツ
ケージの底面図、第２図は第１図実施例のＡ―Ａ
′線断面図、第３図は従来の表面実装型パツケー
ジの底面図、第４図は第３図の表面実装型パツケ
ージのＢ―Ｂ′線断面図である。第５図、第６図
は実装例を示す図である。 １…セラミツクケース、２…外部端子、３…キ
ツプ、４…半導体チツプ、５…金属細線、６…他
表面実装パツケージ収容空間、７…通気隙間。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体チツプを収容する表面実装型パツケージ
    の底部に、他の表面実装型パツケージを収容でき
    る空間を設けたことを特徴とする半導体装置のパ
    ツケージ。
JP1988165403U 1988-12-20 1988-12-20 Pending JPH0284335U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988165403U JPH0284335U (ja) 1988-12-20 1988-12-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988165403U JPH0284335U (ja) 1988-12-20 1988-12-20

Publications (1)

Publication Number Publication Date
JPH0284335U true JPH0284335U (ja) 1990-06-29

Family

ID=31451858

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988165403U Pending JPH0284335U (ja) 1988-12-20 1988-12-20

Country Status (1)

Country Link
JP (1) JPH0284335U (ja)

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