JPH0282628A - Manufacture of vertical mosfet - Google Patents
Manufacture of vertical mosfetInfo
- Publication number
- JPH0282628A JPH0282628A JP63235827A JP23582788A JPH0282628A JP H0282628 A JPH0282628 A JP H0282628A JP 63235827 A JP63235827 A JP 63235827A JP 23582788 A JP23582788 A JP 23582788A JP H0282628 A JPH0282628 A JP H0282628A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- conductivity type
- diffusion layer
- remaining
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000005530 etching Methods 0.000 claims abstract description 19
- 239000012535 impurity Substances 0.000 claims abstract description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 6
- 229920005591 polysilicon Polymers 0.000 claims abstract description 6
- 239000007772 electrode material Substances 0.000 claims abstract 3
- 238000009792 diffusion process Methods 0.000 claims description 35
- 239000000758 substrate Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 229910018125 Al-Si Inorganic materials 0.000 claims description 2
- 229910018520 Al—Si Inorganic materials 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims description 2
- 238000009413 insulation Methods 0.000 claims 2
- 238000000059 patterning Methods 0.000 claims 2
- 238000005468 ion implantation Methods 0.000 abstract description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 2
- 239000011574 phosphorus Substances 0.000 abstract description 2
- 230000001590 oxidative effect Effects 0.000 abstract 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000005484 gravity Effects 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は縦型のＭＯＳＦＥＴに関し、主としてＰチャン
ネルＭＯ５ＦＥＴを対象とする。DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a vertical MOSFET, and mainly targets a P-channel MO5FET.
（ロ）従来の技術
ＮチャンネルＦＥＴにコンプリメンタリ−（相補的）に
組合せ、又は単独の素子として大電流のスイッチング動
作を行わせる目的で、しばしばＰチャンネル型の重力用
ＦＥＴが必要とされている。かかる用途や目的のために
重力用の大電流・高耐圧のＦＥＴを得るには、その特性
上、ドレイン電極が基板となる縦型のＦＥＴが適合して
いる。すなわち第２図に示す如く、裏面にＰ１型層（１
）を有するＰ型半導体基体（２）の主表面に形成したＮ
型拡散層（３）の一部にＰ“型ソース領域（４）とその
電極（５）及びゲート電極（６）を設け、基体（２）の
裏面からドレイン電極（７）を取り出すことにより、単
位面積当りのＦＥＴ動作する活性面積が大きくとれ、そ
の結果ドレインソース間のオン抵抗の低減、相互フンダ
クタンスの増大、したがって電流容量の増大といった目
的が達せられる。(b) Prior Art P-channel gravity FETs are often required for the purpose of performing large current switching operations in complementary combination with N-channel FETs or as a single element. In order to obtain a large-current, high-voltage FET for gravity use for such uses and purposes, a vertical FET in which the drain electrode serves as a substrate is suitable due to its characteristics. That is, as shown in FIG. 2, a P1 type layer (1
) formed on the main surface of the P-type semiconductor substrate (2)
By providing a P" type source region (4), its electrode (5) and gate electrode (6) in a part of the type diffusion layer (3), and taking out the drain electrode (7) from the back surface of the base body (2), The active area for FET operation per unit area can be increased, and as a result, the objectives of reducing the on-resistance between the drain and source, increasing the mutual conductance, and therefore increasing the current capacity can be achieved.
ところで、ソース電極（５）としては取扱いの容易さか
ら一般にアルミニウム（Ａｆｆｉ）又はアルミニウム・
シリコン（Ａｌ−Ｓｉ）が用いられているが、アルミニ
ウムはシリコン（Ｓｉ）に対してＰ型不純物としての特
性を有する為、Ｎ型拡散層（３）とでＰＮ接合によるバ
リア（障壁）を形成し、これが素子の特性を劣化きせる
。By the way, the source electrode (5) is generally made of aluminum (Affi) or aluminum for ease of handling.
Silicon (Al-Si) is used, but since aluminum has characteristics as a P-type impurity with respect to silicon (Si), it forms a barrier with a PN junction with the N-type diffusion layer (3). However, this deteriorates the characteristics of the element.
この様な欠点に対し、同じく第２図に示すようにＮ型拡
散層（３）表面にＮ１型の高濃度コンタクト領域（８）
を形成することによりソース電極（５）とＮ型拡散層（
３）とのオーミック性を改善する技術が特開昭５８−１
６５６９号公報（ＨＯＩＬ ２９／７８）に記載され
ている。To deal with these defects, as shown in Figure 2, an N1-type high concentration contact region (8) is formed on the surface of the N-type diffusion layer (3).
By forming a source electrode (5) and an N-type diffusion layer (
3) The technology to improve the ohmic property with JP-A-58-1
It is described in Publication No. 6569 (HOIL 29/78).
（ハ）発明が解決しようとする課題
しかしながら、Ｐ”型ソース領域（４）とソース電極（
５）とは電流容量を確保する為ある程度のコンタクト面
積を必要とすることから、ホトレジスト処理によりＮ＋
型コンタクト拡散層（８）を選択的に形成することは素
子の微細化を押し進める上で弊害となる欠点を有してい
る。(c) Problems to be solved by the invention However, the P'' type source region (4) and the source electrode (
5) requires a certain amount of contact area to ensure current capacity, so photoresist processing is used to
Selective formation of the type contact diffusion layer (8) has the drawback of being detrimental to the progress of device miniaturization.
（ニ）課題を解決するための手段
本発明は斯上した欠点に鑑み成されたもので、ゲート電
極（１７）材料によってＮ型拡散Ｊｉ（２０）表面に残
存膜（１８）を残し、この残存膜（１８）を利用してセ
ルファライン的にＮ＋型コンタクト拡散ｆｆ（２５）を
形成することにより、微細化に適した縦型ＭＯＳＦＥＴ
の製造方法を提供するものである。(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned drawbacks, and it leaves a residual film (18) on the surface of the N-type diffused Ji (20) using the gate electrode (17) material. A vertical MOSFET suitable for miniaturization is created by forming an N+ type contact diffusion ff (25) in a self-line manner using the remaining film (18).
The present invention provides a method for manufacturing.
くホ）作用
本発明によれば、残存膜（２５）によってＰ＋型ソース
領域（２１）とＮ１型コンタクトＪＧ（２５）との双方
がセルファラインにより形成できるので、マスク合せ精
度が不要となり微細化が可能になる。According to the present invention, both the P+ type source region (21) and the N1 type contact JG (25) can be formed by self-alignment using the remaining film (25), so mask alignment accuracy is not required and miniaturization is possible. becomes possible.
（へ）実施例
以下、本発明の一実施例を図面を参照しながら詳細に説
明する。本発明の目的はこのような縦型のＰチャンネル
電力用ＦＥＴを提供することにある。本発明によるＰｆ
ヤンネルＭＯ５ＦＥＴは第１図（ａ）〜（ｋ）で示す各
工程のプロセスに従って製造される。(F) Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings. An object of the present invention is to provide such a vertical P-channel power FET. Pf according to the invention
The Jannel MO5FET is manufactured according to the steps shown in FIGS. 1(a) to 1(k).
（ａ）まず、Ｂ（ボロン）を高濃度にドープしたＰ４型
Ｓｉ基板（１１）上に低濃度のＰ型エピタキシャル成長
Ｊｌ（１２）を形成したＰ−Ｐ＋型基体（１３）を用意
する。(a) First, a PP+ type substrate (13) is prepared, in which a low concentration P type epitaxial growth Jl (12) is formed on a P4 type Si substrate (11) doped with a high concentration of B (boron).
（ｂ）この基体（１３）表面にホトレジスト処理した酸
化膜（１４）をマスクにして選択的にＮ型のＮ型拡散Ｗ
Ｊ（１５）を形成する。この部分は前記基板に対し部分
的に深く存在させる。(b) Selective N-type diffusion W using the photoresist-treated oxide film (14) on the surface of this substrate (13) as a mask.
Form J(15). This portion is partially deep to the substrate.
（ｃ）シかる後、ゲートとなる部分に熱酸化により新た
にゲート酸化膜（１６）を形成する。このときＦＥＴの
周囲のフィールド部には最初の厚い酸化膜（１４）をそ
のまま残存させる。この後全面にポリシリコン層をデポ
ジットし、ホトレジスト処理によってポリシリコン層を
選択的にエツチング除去することによりゲート酸化膜（
１６）上にはゲート電極（１７）を、Ｎ型拡散層（１５
）上のゲート酸化膜（１６）上には本発明の構成に欠く
ことのできない残存膜（１８）を形成する。(c) After this, a new gate oxide film (16) is formed by thermal oxidation on the portion that will become the gate. At this time, the initial thick oxide film (14) remains in the field area around the FET. After this, a polysilicon layer is deposited on the entire surface, and the gate oxide film (
16) A gate electrode (17) is placed on top of the N-type diffusion layer (15).
) A residual film (18), which is essential to the structure of the present invention, is formed on the gate oxide film (16) on the gate oxide film (16).
（ｄ）続いてゲート電極（１６）と残存膜（１８）をマ
スクとし、チャンネル形成のためのＮ型領域（１９）を
イオン注入又はデポジットと熱拡散により選択的に形成
する。前記熱拡散によりＮ型領域（１９）はゲート電極
（１７）の下部に横方向拡散により廻り込んでチャンネ
ル部を形成し、きらに先に形成した深いＮ型拡散層（１
５）と連結して同図に示す形状のＮ型拡散層（２０）を
形成する。(d) Next, using the gate electrode (16) and the remaining film (18) as a mask, an N-type region (19) for forming a channel is selectively formed by ion implantation or deposition and thermal diffusion. Due to the thermal diffusion, the N-type region (19) spreads around the lower part of the gate electrode (17) in the lateral direction to form a channel part, and the deep N-type region (19) formed earlier forms a channel part.
5) to form an N-type diffusion layer (20) having the shape shown in the figure.
（ｅ）次にゲート電極（１７）と残存膜（１８）を再び
マスクとして、Ｐ＋型ソース領域（２１）をイオン注入
又はデポジットと熱処理によりＮ型拡散Ｊｆｆｉ（２０
）表面に選択的に形成する。結果、Ｐ−型エピタキシへ
・ルＪＷ（１２）とＰ＋型ソース領域（２１）とに挾ま
れたＮ型拡散Ｊｉ（２０）表面がチャンネルとなる。本
工程は残存膜（１８）を利用するので、ホトレジスト工
程は一切必要無い。(e) Next, using the gate electrode (17) and the remaining film (18) as masks again, the P+ type source region (21) is ion-implanted or deposited and heat treated to form an N-type diffused Jffi (20
) selectively formed on the surface. As a result, the surface of the N-type diffused Ji (20) sandwiched between the P- type epitaxial layer JW (12) and the P+ type source region (21) becomes a channel. Since this step utilizes the remaining film (18), no photoresist step is necessary.
（ｆ）その後ゲート電極（１７）と残存膜（１８）を覆
う様にして全面にＣＶＤ（化学反応気相析出）法による
リンドープの絶縁酸化膜（２２ａ）を形成し、全面をパ
ッシベーションすると共に、ゲート電極（１７）による
段差を平坦化する為の５ＯＧ（スピンオングラス）酸化
膜（２２ｂ）を形成する。そして、平坦化した酸化膜（
２１）上にホトレジスト膜（２３）をスピンオン塗布し
、露光・現像することで残存膜（１８）に対応する部分
に開孔部（２４）を有するホトレジスト膜（２３）とす
る。開孔部（２４）は残存膜（１８）パターンと同程度
の大きさか若しくは位置合せ精度を考慮してやや大きな
開孔部（２４）とする。(f) After that, a phosphorus-doped insulating oxide film (22a) is formed on the entire surface by CVD (chemical vapor deposition) so as to cover the gate electrode (17) and the remaining film (18), and the entire surface is passivated. A 5OG (spin-on-glass) oxide film (22b) is formed to flatten the step caused by the gate electrode (17). Then, the planarized oxide film (
21) A photoresist film (23) is spin-on coated on top, exposed and developed to form a photoresist film (23) having openings (24) in portions corresponding to the remaining film (18). The openings (24) are made to be approximately the same size as the remaining film (18) pattern, or slightly larger in consideration of alignment accuracy.
（ｇ）ホトレジスト膜（２３）をマスクとして酸化膜（
２１）をエツチングし、残存膜（１８）周囲の酸化膜（
２１）を残すようにして残存膜（１８）の頭部を露出さ
せる。エツチングにはウェット方式による等方エツチン
グ又はドライ方式による異方又は等方エツチングを用い
る。(g) Using the photoresist film (23) as a mask, the oxide film (
21) and remove the oxide film (18) around the remaining film (18).
21) to expose the top of the remaining membrane (18). For etching, wet isotropic etching or dry anisotropic or isotropic etching is used.
（ｈ）続いてポリシリコン（Ｐｏｌｙ−Ｓｉ）とシリコ
ン酸化膜（ＳｉＯｚ）との選択性を利用して、残存膜（
１８）だけをエツチング除去する。エツチングにはＨＦ
をベースとしたウェット方式の他、ＳＦ６をエツチング
ガスとするＲ Ｉ Ｅ （Ｒｅａｃｔｉｖｅ Ｉｏｎ
Ｅｔｃｈｉｎｇ）によるドライ方式が選択できる。ＲＩ
Ｅでは選択比の高い異方性エツチングができるので、極
めて正確なエツチング除去ができる。(h) Next, using the selectivity between polysilicon (Poly-Si) and silicon oxide film (SiOz), the remaining film (
18) is removed by etching. HF for etching
In addition to the wet method based on
A dry method (Etching) can be selected. R.I.
Since E allows anisotropic etching with a high selectivity, extremely accurate etching removal is possible.
（ｉ）残存膜（１８）を除去した後の酸化膜（２２）の
段差をマスクとしてリン（Ｐ）等の不純物をイオン注入
することにより、ソース領域（２１）の真中部分にＮ＋
型のコンタクト拡散層（２５）を形成する。イオン注入
はＮ型拡散層（２０）表面のゲート酸化膜〈１６）を貫
通して行なわれ、ソース領域（２１）に対して完全なセ
ルファラインにより形成できる。(i) By ion-implanting impurities such as phosphorus (P) using the steps of the oxide film (22) after removing the remaining film (18) as a mask, N+
A mold contact diffusion layer (25) is formed. The ion implantation is performed through the gate oxide film (16) on the surface of the N-type diffusion layer (20), and can be formed by a complete self-alignment with respect to the source region (21).
（ｊ）酸化膜（２１）を開孔してＮ＋型コンタクト拡散
層（２５〉とソース領域（２１）の一部を露出し、ソー
スコンタクト孔とする。(j) A hole is opened in the oxide film (21) to expose a part of the N+ type contact diffusion layer (25>) and the source region (21) to form a source contact hole.
（ｋ）全面にＡｔ又は１％Ｓｉを含むＡｆｉ −Ｓｉの
蒸着によりＮ４型コンタクト拡散層（２５）とＰ＋型ソ
ース領域（２１）の双方にコンタクトするソース電極（
２６）を形成し、ポリシリコン層からはゲート電極Ｇを
取り出し、Ｐ＋基板（１１）裏面からドレインとなるべ
き電極りをＩ’１−Ｎｉ−Ａｇ等の蒸着により取り出す
。(k) A source electrode that contacts both the N4 type contact diffusion layer (25) and the P+ type source region (21) by evaporating Afi-Si containing At or 1% Si on the entire surface (
26) is formed, a gate electrode G is taken out from the polysilicon layer, and an electrode to be a drain is taken out from the back surface of the P+ substrate (11) by vapor deposition of I'1-Ni-Ag or the like.
このようにして製造された本発明のＰチャンネル型の縦
型ＭＯＳＦＥＴは、Ｎ＋型コンタクト拡散層（２５）を
形成することでＮ型拡散層（２０）とソース電極（２１
）との良好なオーミックコンタクトが得られ、Ｎ型拡散
層（２０）の電位が安定して定まるので、ゲート電極（
１７）下にチャンネル（反転層）が安定して形成され、
従って安定したＭＯＳＦＥＴ動作が得られる。The P-channel type vertical MOSFET of the present invention manufactured in this way can be formed by forming an N+ type contact diffusion layer (25), thereby forming an N type diffusion layer (20) and a source electrode (21).
), and the potential of the N-type diffusion layer (20) is stably determined.
17) A channel (inversion layer) is stably formed below,
Therefore, stable MOSFET operation can be obtained.
そして本発明の製造方法によれば、残存膜（１８）を利
用してＮ＋型コンタクト拡散層（２５）をセルファライ
ンにより形成できるので、ゲート電極（１７）との、及
びソース領域（２１）とのマスク合せ余裕を持たせる必
要が無く、従ってパターンサイズを縮小できる。According to the manufacturing method of the present invention, the N+ type contact diffusion layer (25) can be formed by self-line using the remaining film (18), so that it can be connected to the gate electrode (17) and the source region (21). There is no need to provide a margin for mask alignment, and the pattern size can therefore be reduced.
本発明の第２の実施例は、ＳＯＧ酸化膜（２２ｂ）と等
方エツチングを利用することによりソース電極（２６）
の被覆性を改善するものである。In the second embodiment of the present invention, the source electrode (26) is etched by using the SOG oxide film (22b) and isotropic etching.
This improves the coverage of
すなわち、第１図（ｆ）においてＳＯＧ酸化膜（２２ｂ
）を形成することにより残存膜（１８）上の酸化膜（２
１）の膜厚よりソース領域（２１）上の酸化膜（２１）
の膜厚を厚くし、
第１図（ｇ＞において残存膜（１８）より大きく酸化膜
（２１）をエツチングすることで残存膜（１８）頭部が
完全に突出するように露出させ、
第１図（ｈ）において残存膜（１８）を除去することに
より酸化膜（２１）に段差を付け、
第１図（ｊ）において前記段差を等方エツチングするこ
とにより、前記段差による膜厚の薄い部分を除去してソ
ースコンタクト孔とし且つ膜厚の厚い部分は前記等方エ
ツチングにより緩らかな段差に形成し、
第１図（ｋ）においてソース電極（２６）を形成するこ
とにより、ソース電極（２６）の段切れや断線を防止し
た、信頼性の高い縦型ＭＯ３ＦＥＴとすることができる
。That is, in FIG. 1(f), the SOG oxide film (22b
) on the remaining film (18).
The oxide film (21) on the source region (21) is thicker than the film thickness of 1).
By increasing the film thickness of the oxide film (21) and etching the oxide film (21) larger than the remaining film (18) in FIG. In FIG. 1(h), a step is formed in the oxide film (21) by removing the remaining film (18), and in FIG. is removed to form a source contact hole, and the thick part is formed into a gentle step by the above-mentioned isotropic etching, and the source electrode (26) is formed as shown in FIG. 1(k). ) can be made into a highly reliable vertical MO3FET that prevents breakage and disconnection.
（ト）発明の効果
以上に説明した如く、本発明によれば、残存膜〈１８）
を利用することによりゲート電極（１７）とＮ＋型コン
タクト拡散層（２５）、及びソース領域（２１）とＮ′
″型コシコンタクト拡散層５）とをセルファラインによ
り形成できるので、微細化に適した縦型ＭＯ５ＦＥＴの
製造方法を提供できる利点を有する。(g) Effects of the invention As explained above, according to the present invention, residual film <18>
By using
Since the ``type stiff contact diffusion layer 5) can be formed by self-alignment, it has the advantage of providing a method for manufacturing a vertical MO5FET suitable for miniaturization.
また、本発明の第２の実施例によれば、ゲート電極（１
７）側面の酸化膜（２１）を緩らかな段差に形成できる
ので、ソース電極（２６）の段切れや断線を防止した、
信頼性の高い縦型ＭＯＳＦＥＴを提供できる利点をも有
する。Further, according to the second embodiment of the present invention, the gate electrode (1
7) Since the oxide film (21) on the side surface can be formed into a gentle step, breakage and disconnection of the source electrode (26) can be prevented.
It also has the advantage of providing a highly reliable vertical MOSFET.
【図面の簡単な説明】
第１図（ａ）〜（ｋ）は夫々本発明の製造方法を説明す
る為の断面図、第２図は従来例を説明する為の断面図で
ある。BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1K are cross-sectional views for explaining the manufacturing method of the present invention, and FIG. 2 is a cross-sectional view for explaining a conventional example.
Claims (4)
部に不純物を拡散して第２導電型拡散層を形成する工程
、 前記基体表面にゲート絶縁膜を介してゲート電極を形成
すると共に、前記第２導電型拡散層表面の一部に前記ゲ
ート電極材料を残存膜として残す工程、 前記ゲート絶縁膜と前記残存膜をマスクとしてＭＯＳＦ
ＥＴのチャンネル部分を形成する第２導電型の不純物を
拡散する工程、 前記ゲート絶縁膜と前記残存膜を再びマスクとしてＭＯ
ＳＦＥＴのソース領域を形成する第１導電型の不純物を
拡散する工程、 前記ゲート絶縁膜と前記残存膜を覆うように全面を絶縁
膜で覆う工程、 前記絶縁膜上にホトレジスト膜を形成し、パターニング
して前記残存膜に対応する部分を開孔する工程、 前記ホトレジスト膜をマスクとして前記絶縁膜をエッチ
ングすることにより前記残存膜の頭部を露出させる工程
、 前記絶縁膜と残存膜の選択性により前記残存膜だけをエ
ッチング除去する工程、 前記残存膜を除去した後の開孔を利用して第１導電型不
純物を拡散することにより、前記第２導電型拡散層の表
面に第１導電型高濃度コンタクト拡散層を形成する工程
、 前記絶縁膜を開孔して前記高濃度コンタクト拡散層と前
記ソース領域の一部を露出する工程、前記高濃度コンタ
クト拡散層と前記ソース領域の双方にコンタクトするソ
ース電極を形成する工程とを具備することを特徴とする
縦型ＭＯＳＦＥＴの製造方法。(1) A step of diffusing an impurity into a part of the surface of the first conductivity type semiconductor substrate that will become the drain to form a second conductivity type diffusion layer, and forming a gate electrode on the surface of the substrate via a gate insulating film. , leaving the gate electrode material as a residual film on a part of the surface of the second conductivity type diffusion layer; using the gate insulating film and the residual film as a mask to form a MOSFET;
A step of diffusing a second conductivity type impurity to form a channel portion of ET, using the gate insulating film and the remaining film as a mask again, MO
a step of diffusing impurities of a first conductivity type to form a source region of the SFET; a step of covering the entire surface with an insulating film so as to cover the gate insulating film and the remaining film; forming a photoresist film on the insulating film and patterning it; a step of opening a hole in a portion corresponding to the remaining film; a step of exposing a top portion of the remaining film by etching the insulating film using the photoresist film as a mask; a step of etching away only the remaining film, and diffusing a first conductivity type impurity using the openings after removing the remaining film, thereby forming a first conductivity type high impurity on the surface of the second conductivity type diffusion layer; forming a concentrated contact diffusion layer; opening a hole in the insulating film to expose a portion of the high concentration contact diffusion layer and the source region; and contacting both the high concentration contact diffusion layer and the source region. A method for manufacturing a vertical MOSFET, comprising the step of forming a source electrode.
純物を拡散して第２導電型拡散層を形成する工程、 前記基体表面にゲート絶縁膜を介してゲート電極を形成
すると共に、前記第２導電型拡散層表面の一部に前記ゲ
ート絶縁膜材料を残存膜として残す工程、 前記ゲート絶縁膜と前記残存膜をマスクとしてＭＯＳＦ
ＥＴのチャンネル部分を形成する第２導電型の不純物を
拡散する工程、 前記ゲート絶縁膜と前記残存膜を再びマスクとしてＭＯ
ＳＦＥＴのソース領域を形成する第１導電型の不純物を
拡散する工程、 前記ゲート絶縁膜と前記残存膜を覆う様に全面を絶縁膜
で覆い、次いでＳＯＧ絶縁膜により表面を平坦化する工
程、 前記絶縁膜上にホトレジスト膜を形成し、パターニング
して前記残存膜に対応する部分を開孔する工程、 前記ホトレジスト膜をマスクとして前記絶縁膜を前記残
存膜より大きな開孔部でエッチングし、前記残存膜の頭
部を露出させる工程、 前記絶縁膜と残存膜の選択性により前記残存膜だけをエ
ッチング除去する工程、 前記残存膜を除去した後の開孔を利用して第１導電型の
不純物を拡散することにより、前記第２導電型拡散層の
表面に第１導電型コンタクト拡散層を形成する工程、 前記ホトレジスト膜をマスクとして前記絶縁膜を等方エ
ッチングすることにより、前記絶縁膜を平坦化すると共
に前記コンタクト拡散層と前記ソース領域の一部を露出
する工程、 前記高濃度拡散コンタクト拡散層と前記ソース 領域の
双方にコンタクトするソース電極を形成する工程とを具
備することを特徴とする縦型ＭＯＳＦＥＴの製造方法。(2) forming a second conductivity type diffusion layer by diffusing impurities into a part of the surface of the first conductivity type substrate that will become the drain; forming a gate electrode on the surface of the substrate via a gate insulating film; leaving the gate insulating film material as a residual film on a part of the surface of the second conductivity type diffusion layer, using the gate insulating film and the remaining film as a mask to form a MOSFET;
A step of diffusing a second conductivity type impurity to form a channel portion of ET, using the gate insulating film and the remaining film as a mask again, MO
a step of diffusing impurities of a first conductivity type to form a source region of the SFET; a step of covering the entire surface with an insulating film so as to cover the gate insulating film and the remaining film; and then planarizing the surface with an SOG insulating film; forming a photoresist film on the insulating film and patterning it to open a hole in a portion corresponding to the remaining film; using the photoresist film as a mask, etching the insulating film with an opening larger than the remaining film; a step of exposing the top portion of the film; a step of etching away only the remaining film with selectivity between the insulating film and the remaining film; and a step of etching impurities of the first conductivity type using the openings after removing the remaining film. forming a first conductivity type contact diffusion layer on the surface of the second conductivity type diffusion layer by diffusion; flattening the insulation film by isotropically etching the insulation film using the photoresist film as a mask; and a step of exposing a part of the contact diffusion layer and the source region, and a step of forming a source electrode in contact with both the high concentration diffusion contact diffusion layer and the source region. Method of manufacturing type MOSFET.
つ前記ソース電極はＡｌ又はＡｌ−Ｓｉであることを特
徴とする請求項第１項又は第２項に記載の縦型ＭＯＳＦ
ＥＴの製造方法。(3) The vertical MOSF according to claim 1 or 2, wherein the high concentration contact diffusion layer is an N-type region and the source electrode is Al or Al-Si.
ET manufacturing method.
縁膜は酸化膜であり且つ前記残存膜の選択除去はＲＩＥ
による異方性エッチングであることを特徴とする請求項
第１項又は第２項に記載の縦型ＭＯＳＦＥＴの製造方法
。(4) The gate electrode material is polysilicon, the insulating film is an oxide film, and the remaining film is selectively removed by RIE.
3. The method for manufacturing a vertical MOSFET according to claim 1, wherein the method is anisotropic etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63235827A JPH07101741B2 (en) | 1988-09-20 | 1988-09-20 | Method for manufacturing vertical MOSFET |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63235827A JPH07101741B2 (en) | 1988-09-20 | 1988-09-20 | Method for manufacturing vertical MOSFET |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0282628A true JPH0282628A (en) | 1990-03-23 |
| JPH07101741B2 JPH07101741B2 (en) | 1995-11-01 |
Family
ID=16991845
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63235827A Expired - Lifetime JPH07101741B2 (en) | 1988-09-20 | 1988-09-20 | Method for manufacturing vertical MOSFET |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07101741B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07508371A (en) * | 1992-03-20 | 1995-09-14 | シリコニックス インコーポレーテッド | Threshold adjustment in vertical DMOS devices |
| US5511448A (en) * | 1993-10-26 | 1996-04-30 | Mazda Motor Corporation | Power transfer apparatus for four-wheel drive automotive vehicle |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60180163A (en) * | 1984-01-27 | 1985-09-13 | シーメンス・アクチエンゲゼルシヤフト | Semiconductor element and method of producing same |
| JPS62200766A (en) * | 1986-02-28 | 1987-09-04 | Oki Electric Ind Co Ltd | Manufacture of high withstand voltage dsamosfet element |
| JPS62211955A (en) * | 1986-03-12 | 1987-09-17 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS6350069A (en) * | 1986-08-19 | 1988-03-02 | Matsushita Electronics Corp | Manufacture of mos field effect transistor |
| JPS63132481A (en) * | 1986-11-22 | 1988-06-04 | Toshiba Corp | Manufacture of field effect transistor |
-
1988
- 1988-09-20 JP JP63235827A patent/JPH07101741B2/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60180163A (en) * | 1984-01-27 | 1985-09-13 | シーメンス・アクチエンゲゼルシヤフト | Semiconductor element and method of producing same |
| JPS62200766A (en) * | 1986-02-28 | 1987-09-04 | Oki Electric Ind Co Ltd | Manufacture of high withstand voltage dsamosfet element |
| JPS62211955A (en) * | 1986-03-12 | 1987-09-17 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS6350069A (en) * | 1986-08-19 | 1988-03-02 | Matsushita Electronics Corp | Manufacture of mos field effect transistor |
| JPS63132481A (en) * | 1986-11-22 | 1988-06-04 | Toshiba Corp | Manufacture of field effect transistor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07508371A (en) * | 1992-03-20 | 1995-09-14 | シリコニックス インコーポレーテッド | Threshold adjustment in vertical DMOS devices |
| US5511448A (en) * | 1993-10-26 | 1996-04-30 | Mazda Motor Corporation | Power transfer apparatus for four-wheel drive automotive vehicle |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07101741B2 (en) | 1995-11-01 |
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